公开(公告)号：GB2500149A

公开(公告)日：2013-09-11

申请号：GB201311064

申请日：2011-11-18

Applicant: IBM

Inventor： EBBERS JONATHAN P ,  GOODNOW KENNETH J ,  SHUMA STEPHEN G ,  TWOMBLY PETER A

IPC: G06F21/87 ,  G06F21/00 ,  G06F21/70

Abstract: Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure (100) for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro- electrical mechanical structure "MEMS" (105) initially set to a chip enable state. The structure also includes an activation circuit (110) operable to set the MEMS device, (105) to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device (105) is in the error state.

公开(公告)号：DE3879007T2

公开(公告)日：1993-09-16

申请号：DE3879007

申请日：1988-06-21

Applicant: IBM

Inventor： SAVAGLIO ROBERT J ,  TWOMBLY PETER A

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/319 ,  G06F11/22 ,  G06F11/277 ,  G01R31/318 ,  G06F11/26

Abstract: A pulse control circuit (200) for use in treating indeterminate signature increments in an apparatus producing Random Pattern Testing (RPT) signature analysis of digital circuits. A circuit to control clock pulses to processing devices is provided. The circuit includes a counter (210) to produce a count corresponding to the number of clock pulses received, and also a memory (240) which stores clock count values where indeterminate signature increments will be encountered. A comparator (230) compares the actual clock count values with the stored clock count values to produce a control signal. In response to this control signal, clock pulses are normally allowed to pass to a processing device during clock pulse counts at which determinate signature increments are encountered, but are blocked where indeterminate signature increments are encountered.

公开(公告)号：DE3879007D1

公开(公告)日：1993-04-15

申请号：DE3879007

申请日：1988-06-21

Applicant: IBM

Inventor： SAVAGLIO ROBERT J ,  TWOMBLY PETER A

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/319 ,  G06F11/22 ,  G06F11/277 ,  G01R31/318 ,  G06F11/26

Abstract: A pulse control circuit (200) for use in treating indeterminate signature increments in an apparatus producing Random Pattern Testing (RPT) signature analysis of digital circuits. A circuit to control clock pulses to processing devices is provided. The circuit includes a counter (210) to produce a count corresponding to the number of clock pulses received, and also a memory (240) which stores clock count values where indeterminate signature increments will be encountered. A comparator (230) compares the actual clock count values with the stored clock count values to produce a control signal. In response to this control signal, clock pulses are normally allowed to pass to a processing device during clock pulse counts at which determinate signature increments are encountered, but are blocked where indeterminate signature increments are encountered.

公开(公告)号：DE112011103361T5

公开(公告)日：2013-08-01

申请号：DE112011103361

申请日：2011-11-18

Applicant: IBM

Inventor： EBBERS JONATHAN P ,  SHUMA STEPHEN G ,  GOODNOW KENNETH J ,  TWOMBLY PETER A

IPC: G06F21/00

Abstract: Es werden Strukturen und Verfahren zum Durchführen einer zerstörungsfreien und sicheren Deaktivierung von Funktionalität eines integrierten Schaltkreises (IC) bereitgestellt. Eine Struktur (100) zum Ermöglichen einer zerstörungsfreien und sicheren Deaktivierung und Reaktivierung des integrierten Schaltkreises (IC) enthält eine mikroelektromechanische Struktur „MEMS” (105), die zunächst in einen Chipfreigabezustand gesetzt ist. Die Struktur enthält außerdem einen Aktivierungsschaltkreis (110), der steuerbar ist, um die MEMS-Einheit auf der Grundlage einer erkannten vorbestimmten Bedingung des IC in einen Fehlerzustand zu setzen. Der IC wird deaktiviert, wenn sich die MEMS-Einheit (105) im Fehlerzustand befindet.

公开(公告)号：CA1277433C

公开(公告)日：1990-12-04

申请号：CA568583

申请日：1988-06-03

Applicant: IBM

Inventor： SAVAGLIO ROBERT J ,  TWOMBLY PETER A

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/319 ,  G06F11/22 ,  G06F11/277 ,  G06F11/26

Abstract: A processing pulse control circuit for use in treating indeterminate signature increments in an apparatus producing RPT signature analysis of digital circuits. A circuit to control clock pulses to processing devices is provided. The circuit includes a counter to produce a count corresponding to the number of clock pulses received, and also a memory Which stores clock count values where indeterminate signature increments will be encountered. A comparator compares the actual clock count values with the stored clock count values to produce a control signal. In response to this control signal, clock pulses are normally allowed to pass to a processing device during clock pulse counts at which determinate signature increments are encountered, but are blocked where indeterminate signature increments are encountered.