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    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES
    1.
    发明公开
    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES 有权
    具有多存储器结构半导体元件

    公开(公告)号：EP1665344A4

    公开(公告)日：2007-07-18

    申请号：EP04784950

    申请日：2004-09-24

    Applicant: IBM

    Inventor： GOODNOW KENNETH J ,  KAMPF FRANCIS A ,  NORMAN JASON M ,  VENTRONE SEBASTIAN T

    IPC: G06F13/16 ,  G06F12/02

    CPC classification number: G06F12/0284

    Abstract: A structure and method of transferring data on a semiconductor device (2) having a plurality of systems (e.g. 6 and 3). Each system has at least one processing device (e.g. 7) and a local memory structure (e.g. 8). Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

    POWER DOWN PROCESSING ISLANDS
    2.
    发明公开
    POWER DOWN PROCESSING ISLANDS 有权
    POWER DOWN处理岛

    公开(公告)号：EP1644964A4

    公开(公告)日：2008-07-30

    申请号：EP04778016

    申请日：2004-07-09

    Applicant: IBM

    Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

    IPC: G11C16/04 ,  G06F1/32 ,  G11C5/14 ,  G11C19/08 ,  H01L20060101

    CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

    Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

    SYSTEM AND METHOD FOR DYNAMICALLY EXECUTING A FUNCTION IN A PROGRAMMABLE LOGIC ARRAY
    3.
    发明公开
    SYSTEM AND METHOD FOR DYNAMICALLY EXECUTING A FUNCTION IN A PROGRAMMABLE LOGIC ARRAY 审中-公开
    动态系统和方法运行的函数在可编程逻辑阵列

    公开(公告)号：EP1673867A4

    公开(公告)日：2007-07-18

    申请号：EP04795023

    申请日：2004-10-13

    Applicant: IBM

    Inventor： GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

    IPC: H03K19/173 ,  G06F15/78 ,  H03K19/177

    CPC classification number: H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

    Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

    POWER DOWN PROCESSING ISLANDS
    5.
    发明申请
    POWER DOWN PROCESSING ISLANDS 审中-公开
    断电处理岛

    公开(公告)号：WO2005008732A3

    公开(公告)日：2007-07-05

    申请号：PCT/US2004022267

    申请日：2004-07-09

    Applicant: IBM ,  BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

    Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

    IPC: G11C16/04 ,  G11C19/08 ,  H01L20060101

    CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

    Abstract: A structure for processing data on a semiconductor device comprising an input island (14), a processing island (8), and an output island (12) formed on the semiconductor device (18). The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

    Abstract translation: 一种用于在半导体器件上处理数据的结构，包括形成在半导体器件（18）上的输入岛（14），处理岛（8）和输出岛（12）。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

    8.
    发明专利
    未知

    公开(公告)号：DE602004015125D1

    公开(公告)日：2008-08-28

    申请号：DE602004015125

    申请日：2004-09-24

    Applicant: IBM

    Inventor： GOODNOW KENNETH J ,  KAMPF FRANCIS A ,  NORMAN JASON M ,  VENTRONE SEBASTIAN T

    IPC: H01L21/00 ,  G06F12/02

    Abstract: A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

    9.
    发明专利
    未知

    公开(公告)号：DE602004020620D1

    公开(公告)日：2009-05-28

    申请号：DE602004020620

    申请日：2004-07-09

    Applicant: IBM

    Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

    IPC: H01L21/00 ,  G06F1/32 ,  G11C5/14 ,  G11C19/08 ,  H01L20060101

    Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES
    10.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES 审中-公开
    包含大量存储器结构的半导体器件

    公开(公告)号：WO2005031804A3

    公开(公告)日：2006-07-20

    申请号：PCT/US2004031323

    申请日：2004-09-24

    Applicant: IBM ,  GOODNOW KENNETH J ,  KAMPF FRANCIS A ,  NORMAN JASON M ,  VENTRONE SEBASTIAN T

    Inventor： GOODNOW KENNETH J ,  KAMPF FRANCIS A ,  NORMAN JASON M ,  VENTRONE SEBASTIAN T

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/36

    CPC classification number: G06F12/0284

    Abstract: A structure and method of transferring data on a semiconductor device (2) having a plurality of systems (e.g. 6 and 3). Each system has at least one processing device (e.g. 7) and a local memory structure (e.g. 8). Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

    Abstract translation: 在具有多个系统（例如6和3）的半导体器件（2）上传送数据的结构和方法。 每个系统具有至少一个处理设备（例如7）和本地存储器结构（例如8）。 每个处理设备电耦合到每个系统内的每个本地存储器结构。 每个本地存储器结构电耦合到每个其他本地存储器结构。 每个本地存储器结构适于与每个处理设备共享地址空间。 每个处理设备适于将数据和指令传送到每个本地存储器结构。

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