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公开(公告)号：DE68924261T2
公开(公告)日：1996-03-21
申请号：DE68924261
申请日：1989-06-22
Applicant: IBM
Inventor： UNGERBOECK GOTTFRIED DR
IPC: H04B3/23
Abstract: In the echo-cancelling device of the invention new decision-error directed algorithms are developed which permit to maintain adaptivity of the echo coefficients and perform precise tracking of the far-end echo phase in a computationally efficient manner during full-duplex operation. The echo-cancelling device comprises an adjust device (40) performing the minimization of the mean-square error obtained as the difference between the signal at the output of the equalizer (Z) and the data-symbol decision (â), for providing the adjustment of the near echo estimator (20) coefficients, of the far echo estimator (22) coefficients, and of the phase (26) of the estimated far echo.
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公开(公告)号：DE3066889D1
公开(公告)日：1984-04-12
申请号：DE3066889
申请日：1980-12-23
Applicant: IBM
Inventor： UNGERBOECK GOTTFRIED DR , CHEVILLAT PIERRE DR
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公开(公告)号：DE69027531D1
公开(公告)日：1996-07-25
申请号：DE69027531
申请日：1990-09-28
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , UNGERBOECK GOTTFRIED DR , BLANC ALAIN
Abstract: Data circuit terminating equipment DCE (100) which allows the connection of a Data terminal equipment DTE (63) to a telecommunication line and which includes timing arrangements circuits for particularly providing the DTE with transmitter signal element timing (114) and receiver signal element timing (115). The DCE includes processing means (61) for computing a sequence of digital values A(n) and means (60, 23, 22) for deriving from said sequence of digital values A(n) a corresponding sequence of interrupt signals T(n). The DCE further includes timing arrangement circuits (69, 70, 71) for generating a set of N timing pulses at the nominal rate on the occurrence of one interrupt signal T(n). By controlling the generation of the sequence of digital values, the processing means (61) can control the frequency, the phase of every clock generated by the timing arrangements circuits. The receiver signal element timing, the transmitter signal element timing the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are controlled by different sequence of digital values computed by the processing means. By generating appropriate sequences of digital values, the processing means can provide any relationship between the different clocks: a transmit signal element timing being slaved on the receiver signal element timing in a synchronous mode, on an external clock in a tailing mode. The timing arrangement circuits can also provide a transmit sampling clock slaved on the receive sampling clock in order to perform powerful digital echo cancellation techniques. More generally, the processing means (61) can provide any relationship between two determined clocks. Moreover, the DCE including a DTE receive interface circuit 21 transmitting a set of N receive data at the nominal receive clock rate and maintaining the N data bit until the next interrupt signal, the processing means can control the length of the Nth bit, which when a STOP bit can allow the compensation of the DTE and the line data throughput difference.
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公开(公告)号：DE68924261D1
公开(公告)日：1995-10-19
申请号：DE68924261
申请日：1989-06-22
Applicant: IBM
Inventor： UNGERBOECK GOTTFRIED DR
IPC: H04B3/23
Abstract: In the echo-cancelling device of the invention new decision-error directed algorithms are developed which permit to maintain adaptivity of the echo coefficients and perform precise tracking of the far-end echo phase in a computationally efficient manner during full-duplex operation. The echo-cancelling device comprises an adjust device (40) performing the minimization of the mean-square error obtained as the difference between the signal at the output of the equalizer (Z) and the data-symbol decision (â), for providing the adjustment of the near echo estimator (20) coefficients, of the far echo estimator (22) coefficients, and of the phase (26) of the estimated far echo.
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公开(公告)号：DE68915762T2
公开(公告)日：1994-12-08
申请号：DE68915762
申请日：1989-08-21
Applicant: IBM
Inventor： UNGERBOECK GOTTFRIED DR
Abstract: For a modem receiver using an adaptive equalizer with fractional tap spacing, method and apparatus are disclosed for controlling the sample-timing phase. By evaluating bandedge components of the received signal in a particular way, a timing-phase vector signal is derived which is independent of the signal energy at the bandedges and of the quality of frequency separation of the filters for the bandedge signals. After an initial period, the current timing-phase vector signal is captured and stored as a reference. Thereafter, the sampling phase of the receiver is kept at its initial random value, represented by the stored reference timing-phase vector. The necessity to initially change the sampling phase in the receiver to a value which is forced by the received signal is avoided.
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Patent Agency Ranking
公开(公告)号：DE3577167D1
公开(公告)日：1990-05-17
申请号：DE3577167
申请日：1985-08-28
Applicant: IBM
Abstract: For adaptively adjusting the gain in a modem receiver comprising two amplifiers (15, 19), the following steps are performed: for a buffer (21), a Hilbert filter (23), and an equalizer (27), a respective energy indicator (p 2 max , u 2 avg , x 2 avg ) is generated from the signal samples in the respective delay line. Each energy indicator is compared to an associated upper target level (4L u , 3Lp, 1.19 L x ), and for the equalizer also to an associated lower target level - (0.84 L x ). If necessary, a gain correction factor (S) initially set to 1.0 is modified to obtain an overall gain that keeps delay line energies within desired targets. Target comparisons are made so that excess energy in the buffer or Hilbert filter result in a rapid gain reduction whereas average equalizer energy is used for slow adaptations.After a gain change, all acquired samples in the delay lines are also multiplied by the correction factor (S) so that none is lost during gain acquisition. Gain is distributed between the two amplifiers in a swapping operation without modifying the adjusted overall gain.
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7.发明专利
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公开(公告)号：CH609510A5
公开(公告)日：1979-02-28
申请号：CH780076
申请日：1976-06-18
Applicant: IBM
Inventor： CSAJKA ISTVAN , UNGERBOECK GOTTFRIED DR
Abstract: A method and structure for converting a sequence of binary digits into a sequence of discrete signal values, e.g., phase values, of a modulated carrier signal for data transmission. By introducing additional redundant signal values and coding information in a state-dependent sequential manner, enlarged minimum Euclidian distance between possible signal value sequences is achieved which results in a reduced error probability when maximum-likelihood decoding is applied in the receiver.
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公开(公告)号：DE69225715T2
公开(公告)日：1999-02-18
申请号：DE69225715
申请日：1992-12-10
Applicant: IBM
Inventor： UNGERBOECK GOTTFRIED DR
Abstract: This invention concerns a method for the fast start-up of modems for full-duplex data transmission over the Public Switched Telephone Network (PSTN). The start-up time for typical current generation modems as specified in CCITT Recommendations V.32 and V.32bis is about 4 to 8 seconds. This invention allows to shorten that start-up time to about 0.5 to 1 second by applying interleaved and overlapping sending and receiving operations of two connected modems, the calling modem and the answering modem. In brief, both modems send and receive simultaneously in a predetermined sequence at different frequency ranges channel probing tones (e.g. for evaluating the channel bandwidth), repetitive identification messages (e.g. for determining reference times, identifying modulation rates and center frequencies), repetitive response messages (e.g. for transmitting the determined bandwidths and reference times to the other modem and determining round-trip delays), and training sequences (e.g. for determining echoes, frequency shifts, and receiver settings). The modems will then transmit data in a full-duplex mode at the modulation rate and center frequency appropriate for the channel and at an initial bit rate. The maximum achievable bit rate may be achieved later during the full-duplex transmission through rate negotiations.
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公开(公告)号：DE69225715D1
公开(公告)日：1998-07-02
申请号：DE69225715
申请日：1992-12-10
Applicant: IBM
Inventor： UNGERBOECK GOTTFRIED DR
Abstract: This invention concerns a method for the fast start-up of modems for full-duplex data transmission over the Public Switched Telephone Network (PSTN). The start-up time for typical current generation modems as specified in CCITT Recommendations V.32 and V.32bis is about 4 to 8 seconds. This invention allows to shorten that start-up time to about 0.5 to 1 second by applying interleaved and overlapping sending and receiving operations of two connected modems, the calling modem and the answering modem. In brief, both modems send and receive simultaneously in a predetermined sequence at different frequency ranges channel probing tones (e.g. for evaluating the channel bandwidth), repetitive identification messages (e.g. for determining reference times, identifying modulation rates and center frequencies), repetitive response messages (e.g. for transmitting the determined bandwidths and reference times to the other modem and determining round-trip delays), and training sequences (e.g. for determining echoes, frequency shifts, and receiver settings). The modems will then transmit data in a full-duplex mode at the modulation rate and center frequency appropriate for the channel and at an initial bit rate. The maximum achievable bit rate may be achieved later during the full-duplex transmission through rate negotiations.
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