中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.015 seconds)

    STRUCTURE AND PROCESS FOR DISSIPATING HEAT IN HIGH PERFORMANCE CHIP
    2.
    发明专利
    STRUCTURE AND PROCESS FOR DISSIPATING HEAT IN HIGH PERFORMANCE CHIP 失效

    公开(公告)号：JP2001085584A

    公开(公告)日：2001-03-30

    申请号：JP2000251872

    申请日：2000-08-23

    Applicant: IBM

    Inventor： UZOH CYPRIAN E ,  DANIEL C EDELSTEIN

    IPC: H01L23/40 ,  H01L23/34 ,  H01L23/36 ,  H01L23/373

    Abstract: PROBLEM TO BE SOLVED: To enhance thermal conductivity by bonding a semiconductor chip and a heat sink through composite solder containing lead tin solder and one thermal conductivity filling material. SOLUTION: An SOI structure 23 is formed on a silicon substrate 21 and silicon/dielectric/interconnection 25 is formed thereon. A chromium bonding layer 29 is then formed on the silicon substrate 21 on the side opposite to the SOI structure 23 and a nickel or nickel containing layer 31 is formed on the chromium layer 29. Subsequently, a gold layer 33 is formed on the nickel layer 31 and a composite solder layer 35 is provided thereon. The silicon substrate 21 is connected with a copper or tungsten heat sink 37 through solder and bonded to a connection 27 and the rear metallization of the semiconductor chip through the composite solder 35. It is employed in an electronic package including a high performance microprocessor chip and functions as a useful composite solder containing lead tin solder and a thermal conductivity filling material.

    METHOD FOR SELECTIVELY FILLING RECESSED PART WITH CONDUCTIVE METAL
    3.
    发明专利
    METHOD FOR SELECTIVELY FILLING RECESSED PART WITH CONDUCTIVE METAL 失效

    公开(公告)号：JPH11260824A

    公开(公告)日：1999-09-24

    申请号：JP893499

    申请日：1999-01-18

    Applicant: IBM

    Inventor： UZOH CYPRIAN E ,  GRECO STEPHEN E

    IPC: C25D5/02 ,  C23C18/31 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To provide a method for permitting increase in the throughput by reducing a time required for CMP of a plated damascene structure. SOLUTION: An electric insulation layer 3 is provided on a semiconductor board and inside a recessed part. Then, a conductive barrier layer 4 is formed on the insulation layer 3, and a plating seed layer 6 is provided on the barrier layer 4, a photoresist 7 is attached on the plating seed layer 6 and patterned, an insulated horizontal part is planarized by removing a horizontal part of the seed layer 6 between the recessed parts, the photoresist 7 remaining inside the recessed part is removed and plating is applied on the seed layer 6 alone by performing electric plating for the patterned seed layer 6 with a conductive metal by the use of the barrier layer 4 which transmits current during electric plating.

    METHOD FOR PLATING METAL IN SUBMICRON STRUCTURE
    5.
    发明专利
    METHOD FOR PLATING METAL IN SUBMICRON STRUCTURE 失效

    公开(公告)号：JP2001077053A

    公开(公告)日：2001-03-23

    申请号：JP2000227035

    申请日：2000-07-27

    Applicant: IBM

    Inventor： UZOH CYPRIAN E ,  PETER S LOCKE

    IPC: C25D7/12 ,  H01L21/288 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To plate a metal in a submicron structure by sticking a seed layer on the surface of a submicron structure, and annealing the seed layer at a specified temperature before a metal is plated on the seed layer. SOLUTION: A seed layer 1 is allowed to stick to the surface of submicron structure, and the seed layer 1 is annealed at about 80-130 deg.C. Then a metal is plated on the seed layer 1. The annealing is performed during sticking to the seed layer 1 or after completion of it. The seed layer 1 is allowed to stick by sputtering regardless of whether annealing is performed during sticking of the seed layer 1 or after completion. Annealing is typically performed at about 80-130 deg.C, however, it is performed below 120 deg.C. Any annealing temperature can be controlled to control the resistivity of the formed seed layer 1.

    6.
    发明专利
    未知

    公开(公告)号：DE69836313T2

    公开(公告)日：2007-04-19

    申请号：DE69836313

    申请日：1998-12-01

    Applicant: IBM

    Inventor： UZOH CYPRIAN E ,  GRECO STEPHEN E

    IPC: C25D5/02 ,  H01L21/768 ,  C23C18/31 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205

    Abstract: Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

    7.
    发明专利
    未知

    公开(公告)号：DE69836313D1

    公开(公告)日：2006-12-14

    申请号：DE69836313

    申请日：1998-12-01

    Applicant: IBM

    Inventor： UZOH CYPRIAN E ,  GRECO STEPHEN E

    IPC: C25D5/02 ,  H01L21/768 ,  C23C18/31 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205

    Abstract: Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

Patent Agency Ranking