公开(公告)号：EP2047506A4

公开(公告)日：2012-04-25

申请号：EP07783916

申请日：2007-05-18

Applicant: IBM

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1883957A4

公开(公告)日：2008-09-17

申请号：EP06760152

申请日：2006-05-19

Applicant: IBM

Inventor： GRECO STEPHEN E ,  STANDAERT THEODORUS E

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed, hi one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit (102) using a dual damascene structure (124) in a first dielectric layer (110), and BEOL wiring over a second circuit (104) using a single damascene via structure (126) in the first dielectric layer (110). Then, simultaneously generating BEOL wiring over the first circuit (102) using a dual damascene structure (220) in a second dielectric layer (150), and BEOL wiring over the second circuit (104) using a single damascene line wire structure (160) in the second dielectric layer (150). The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.

公开(公告)号：WO2008016740A3

公开(公告)日：2008-06-26

申请号：PCT/US2007069219

申请日：2007-05-18

Applicant: IBM ,  STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在所述ILD材料中形成一个或多个通孔开口; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬里; 在由所述第一衬里覆盖的所述一个或多个通孔开口中的至少一个的顶部上创建一个或多个沟槽开口; 以及形成覆盖沟槽开口和第一衬里的至少一部分的第二衬里。 还提供了由该方法形成的互连结构。

公开(公告)号：JP2004336051A

公开(公告)日：2004-11-25

申请号：JP2004136335

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  GRECO STEPHEN E ,  KWIETNIAK KEITH T ,  SEO SOON-CHEON ,  YANG CHIH-CHAO ,  WANG YUN-YU ,  WONG KWONG H

IPC: H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure.
SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned structure. The insulating layer includes the pore along the surface area of the insulating layer contacting to the liner, and further, the pore is only existent along the surface area contacting to the liner (where the liner is non-existent inside the pore).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在集成电路结构中形成布线层的方法。 解决方案：形成有机绝缘层，对绝缘层进行图案化，在绝缘层上积累衬垫，将上述结构暴露在等离子体中，并且在邻近的区域的绝缘层中形成孔 衬垫。 衬垫形成得足够薄，使得等离子体穿透衬垫，并且在绝缘层上形成孔而不影响衬垫。 在等离子体处理期间，等离子体渗透衬垫而不影响衬套。 在等离子体处理之后，可以累积额外的衬垫。 此后，导体被累积，导体的过多部分从结构中删除。 该方法产生包括具有图案化结构的有机绝缘层，覆盖图案化结构的后侧的衬垫和填充图案化结构的导体的集成电路结构。 绝缘层包括沿着与衬垫接触的绝缘层的表面积的孔，此外，孔沿着与衬垫接触的表面区域（其中衬里不存在于孔内）存在。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11260824A

公开(公告)日：1999-09-24

申请号：JP893499

申请日：1999-01-18

Applicant: IBM

Inventor： UZOH CYPRIAN E ,  GRECO STEPHEN E

IPC: C25D5/02 ,  C23C18/31 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for permitting increase in the throughput by reducing a time required for CMP of a plated damascene structure. SOLUTION: An electric insulation layer 3 is provided on a semiconductor board and inside a recessed part. Then, a conductive barrier layer 4 is formed on the insulation layer 3, and a plating seed layer 6 is provided on the barrier layer 4, a photoresist 7 is attached on the plating seed layer 6 and patterned, an insulated horizontal part is planarized by removing a horizontal part of the seed layer 6 between the recessed parts, the photoresist 7 remaining inside the recessed part is removed and plating is applied on the seed layer 6 alone by performing electric plating for the patterned seed layer 6 with a conductive metal by the use of the barrier layer 4 which transmits current during electric plating.

公开(公告)号：JP2003218109A

公开(公告)日：2003-07-31

申请号：JP2003003569

申请日：2003-01-09

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  ANAND MINAKSHISUNDARAN B ,  ARMACOST MICHAEL D ,  CHEN SHYNG-TSONG ,  GATES STEPHEN M ,  GRECO STEPHEN E ,  KARECKI SIMON M ,  NITTA SATYANARAYANA V

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metallic pattern on a low-dielectric constant substrate. SOLUTION: A hard mask including a lower hard mask layer 31 and an upper hard mask layer 20 is prepared. The upper hard mask layer 20 is a sacrifice layer of about 200 Å thick, which is preferably made of high-melting-point nitride. The sacrifice layer functions as a stop layer in the following CMP metal removal process. A resist layer is used to perform patterning. A protection layer 31t is formed on a hard mask, or a non-oxidized resist strip process is used, so as to avoid the damage of oxidization to the lower hard mask layer 31. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001024060A

公开(公告)日：2001-01-26

申请号：JP2000139087

申请日：2000-05-11

Applicant: IBM

Inventor： ROBERT COOK ,  GRECO STEPHEN E ,  JOHN P HUMMEL ,  JOYCE RYUU ,  MCGAHAY VINCENT J ,  REBECCA MEE ,  SRIVASTAVA KAMALESH

IPC: G03F7/40 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent invasion with a developer of SSQ dielectric material during the resist pattern formation by forming another resist pattern on the surface of an intermediate material, and then removing a part of the intermediate material and the other part of such material depending on the other resist pattern. SOLUTION: An etching process is executed to form an aperture 22' to a thin oxide layer 16 as an intermediate material depending on a pattern 20 generated in the resist 18 and also to form a recess 22 to the SSQ (silsesquioxane material) layer 14. The other resist layer 24 is coated on the surface of the oxide layer 16. This resist layer 24 is then exposed and developed to form a resist pattern 26. Moreover, depending on the pattern 26, it is then developed to generate an undercut 28' of a via resist 24. Thereafter, the via 27 is formed with the unisotropic etching process. As a result, while the resist pattern 26 is formed, the pattern is never invaded with the developer owing to the SSQ material.

公开(公告)号：DE602006013303D1

公开(公告)日：2010-05-12

申请号：DE602006013303

申请日：2006-05-19

Applicant: IBM

Inventor： GRECO STEPHEN E ,  STANDAERT THEODORUS E

IPC: H01L21/4763 ,  H01L23/528

Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.

公开(公告)号：DE69836313D1

公开(公告)日：2006-12-14

申请号：DE69836313

申请日：1998-12-01

Applicant: IBM

Inventor： UZOH CYPRIAN E ,  GRECO STEPHEN E

IPC: C25D5/02 ,  H01L21/768 ,  C23C18/31 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205

Abstract: Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

公开(公告)号：DE69323628T2

公开(公告)日：1999-09-30

申请号：DE69323628

申请日：1993-04-29

Applicant: IBM

Inventor： GRECO STEPHEN E ,  SRIKRISHNAN KRIS

IPC: H01L21/768 ,  H01L23/12 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

Abstract: An integrated circuit having organic dielectric between interconnection layers eliminates damage caused by vapors outgassing from the organic dielectric by the use of a two-component organic layer having a breathable etch resistant organic layer above the main organic dielectric layer, both of the organic layers remaining in the final circuit. The etch resistant layer is resistant to the etchant used to pattern the layer of interconnect above the organic dielectric.