公开(公告)号：JP2008072153A

公开(公告)日：2008-03-27

申请号：JP2007316155

申请日：2007-12-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAYNES MICHAEL ,  VIERO GIORGIO ,  OGGIONI STEFANO

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L24/28 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To conduct lid mounting optimized for an electronic device and a carrier that optimizes heat dissipation and electromagnetic interference shielding. SOLUTION: Optimized lid mounting for an electronic device and a carrier which uses standard manufacturing process steps of semiconductor packaging, and optimizes heat dissipation and electromagnetic interference shielding is disclosed. According to the present invention, conductive blocks or springs are soldered to ground pads of the chip carrier on rear surfaces thereof. On other surfaces, these conductive blocks or springs are electrically connected to a lid using a conductive adhesive material such as a silicone based material. Further, the lid is thermally connected to the semiconductor chip by an electrically insulating adhesive material. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为优化散热和电磁干扰屏蔽的电子设备和载体进行优化的盖子安装。 解决方案：公开了一种使用半导体封装的标准制造工艺步骤的电子器件和载体的优化盖安装，并且优化了散热和电磁干扰屏蔽。 根据本发明，将导电块或弹簧焊接到其后表面上的芯片载体的接地焊盘。 在其它表面上，这些导电块或弹簧使用诸如硅酮基材料的导电粘合剂材料电连接到盖子。 此外，盖子通过电绝缘的粘合剂材料热连接到半导体芯片。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004235617A

公开(公告)日：2004-08-19

申请号：JP2003421713

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAYNES MICHAEL ,  VIERO GIORGIO ,  OGGIONI STEFANO

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/34 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L24/28 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide an optimized lid mounting for electronic device and carrier which optimizes thermal radiation and electromagnetic interference shielding. SOLUTION: A conductive block or spring is soldered to the ground pad of a chip carrier at the lower face of these. The conductive block or spring is electrically connected to the lid on the other face, by using a conductive adhesive like a silicone based material. Further, the lid is thermally connected to a semiconductor chip by an electrically insulating adhesive. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：AU2003276277A1

公开(公告)日：2004-03-03

申请号：AU2003276277

申请日：2003-04-18

Applicant: IBM

Inventor： CASTRIOTTA MICHELE ,  OGGIONI STEFANO ,  ROGIANI GIANLUCA ,  SPREAFICO MAURO ,  VIERO GIORGIO

IPC: H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11

Abstract: A stacked via structure ( 200 ) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks ( 205 a, 205 b, 205 c) belonging to three adjacent conductive layers ( 110 a, 110 b, 110 c) separated by dielectric layers ( 120 ), aligned according to z axis. Connections between these conductive tracks are done with at least two vias ( 210, 215 ) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.

公开(公告)号：DE60314868T2

公开(公告)日：2008-03-13

申请号：DE60314868

申请日：2003-04-18

Applicant: IBM

Inventor： CASTRIOTTA MICHELE ,  OGGIONI STEFANO ,  ROGIANI GIANLUCA ,  SPREAFICO MAURO ,  VIERO GIORGIO

IPC: H05K1/11 ,  H01L23/498 ,  H05K3/46 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02

Abstract: A stacked via structure ( 200 ) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks ( 205 a, 205 b, 205 c) belonging to three adjacent conductive layers ( 110 a, 110 b, 110 c) separated by dielectric layers ( 120 ), aligned according to z axis. Connections between these conductive tracks are done with at least two vias ( 210, 215 ) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.

公开(公告)号：DE60314868D1

公开(公告)日：2007-08-23

申请号：DE60314868

申请日：2003-04-18

Applicant: IBM

Inventor： CASTRIOTTA MICHELE ,  OGGIONI STEFANO ,  ROGIANI GIANLUCA ,  SPREAFICO MAURO ,  VIERO GIORGIO

IPC: H05K1/11 ,  H01L23/498 ,  H05K3/46 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02

Abstract: A stacked via structure ( 200 ) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks ( 205 a, 205 b, 205 c) belonging to three adjacent conductive layers ( 110 a, 110 b, 110 c) separated by dielectric layers ( 120 ), aligned according to z axis. Connections between these conductive tracks are done with at least two vias ( 210, 215 ) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.

公开(公告)号：AT367077T

公开(公告)日：2007-08-15

申请号：AT03787806

申请日：2003-04-18

Applicant: IBM

Inventor： CASTRIOTTA MICHELE ,  OGGIONI STEFANO ,  ROGIANI GIANLUCA ,  SPREAFICO MAURO ,  VIERO GIORGIO

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02

Abstract: A stacked via structure ( 200 ) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks ( 205 a, 205 b, 205 c) belonging to three adjacent conductive layers ( 110 a, 110 b, 110 c) separated by dielectric layers ( 120 ), aligned according to z axis. Connections between these conductive tracks are done with at least two vias ( 210, 215 ) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.