公开(公告)号：DE2000565A1

公开(公告)日：1970-07-23

申请号：DE2000565

申请日：1970-01-07

Applicant: IBM

Inventor： CRAIG BOSSEN DOUGLAS ,  HSIAO MU-YUE ,  FAIRBANKS SELLERS JUN FREDERIC ,  TIENWEN CHIEN ROBERT

IPC: H03M13/19 ,  H04L1/00 ,  H04L1/10

Abstract: 1,247,823. Error-correcting systems. INTERNATIONAL BUSINESS MACHINES CORP., and ROBERT TIENWEN CHIEN. 8 Jan., 1970 [8 Jan., 1969], No. 1041/70. Heading G4A. A message containing k data bits has 2m check bits added to it (k#m 2 , where m=integer greater than 1) for each of t error-correcting capabilities (t#1), and a decoder comprises t parity-checking circuits supplying outputs to an error-correcting circuit for that bit. As an example, where k=25 and m=5, the message bits d 0 -d 24 are considered arranged as a 5 x 5 matrix, check bits c 1 -c 5 are derived by exclusive OR operation on the matrix rows (e.g. c 1 =EXOR (do, d 1 , d 2 , d 3 , d 4 ) and check bits c 6 -c 10 are similarly derived from the matrix columns (e.g. c 6 =EXOR d 0 , d 5 , d 10 , d 15 , d 20 ) to provide for single error correction. For each additional error correction capability, a pair of orthogonal Latin squares such as L 1 , L 2 and L 3 , L 4 , Fig. 4, is used to select two groups of 5 bits from the matrix, each group comprising bits located in positions marked with the same number in the Latin squares, the additional check bits c 11 -c 15 (L 1 ), C 16 -C 20 (L 2 ) again being derived by exclusive OR operation on the 5 selected bits. Each bit d 0 -d 24 therefore occurs in only two of the equations defining each set of mt check bits. For each bit, such as d 0 , the error-correcting decoder comprises a module I-III, Fig. 5, for each error-correcting capability, each module consisting of a pair of exclusive OR circuits such as 30, 32 receiving inputs corresponding to the check bit equations in which that bit occurs, e.g. for do circuit 30 has inputs d 1 -d 4 and c 1 . Each circuit 30, 32 provides an output which should be a copy of the corresponding bit, and these copies, together with the original bit are supplied to a majority logic gate 38 to provide a corrected output, assuming not more than the number of random errors allowed for have occurred. For the ease where k

公开(公告)号：DE1474046A1

公开(公告)日：1971-04-08

申请号：DE1474046

申请日：1964-10-23

Applicant: IBM

Inventor： TIENWEN CHIEN ROBERT ,  VISVALD FREIMAN CHARLES

IPC: G06F17/30 ,  G06F9/00

Abstract: 1,051,786. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 30, 1964 [Oct. 23. 1963]. No. 39741/64. Headings G4A and G4C. A data item is stored at an address depending on the remainder from a division of a key identifying the item by an m-th order polynomial, m being less than the number of digits in each key, the series of digits of a key belonging to an algebraic ring with a unit element to which the coefficients of the polynomial also belong. Referring to Fig. 1, data on lines 18b from an information processor 12 can be stored in a file memory 16 together with a key identifying it (on lines 18a) at that unused location whose address is closest to, but not less than, an address derived from the key in a circuit 14. To retrieve data, the key is applied to circuit 14 and the resulting address used to address memory 16 as before. The keys stored in the addressed location and subsequent locations are compared in turn with the required key present on lines 18a, and the data read out on to lines 18b on a match being obtained. The key-to-address transformation circuit 14 receives the key serially on line 26, augments (if necessary) its length to an integral multiple of m bits, performs the division referred to and produces the remainder (the address) on line 28. The first and last bits of the key on line 26 are indicated by first and second pulses L on line 27 to control circuit 20. The first of these produces an output from modulo-2 adder 72 which via an (m- 1) bit delay 88 sets a flip-flop 112 to enable AND-gate 42 in circuit 14 (see Fig. 1) and which also resets modulo-m counter 92 which counts bit-timing signals on line CP. The second pulse L triggers (m - 1)-bit astable multivibrator 78 which thereupon enables AND-gate 98 for an interval of (m - 1) bit times. The first output from modulo-m counter 92 during this interval resets flip-flop 112, thus (by a signal on line 32) shifting the contents of delay line 38 an m-bit shift register 62, the output of which (in parallel) is used for addressing the memory 16. If a new first-bit signal L arrives while flip-flop 112 is still set, an alarm signal is produced on line 66. The file memory 16 may consist of microfilm or magnetic tape. If all keys are of the same (appropriate) length, units 78. 92, 98 may be dispensed with and line 76 connected directly to line 104.

公开(公告)号：DE1474359A1

公开(公告)日：1969-05-14

申请号：DE1474359

申请日：1965-04-08

Applicant: IBM

Inventor： TIENWEN CHIEN ROBERT

IPC: G06F7/72 ,  H03M13/15 ,  H03K13/34

公开(公告)号：DE1774953A1

公开(公告)日：1972-05-04

申请号：DE1774953

申请日：1965-04-08

Applicant: IBM

Inventor： TIENWEN CHIEN ROBERT

IPC: H03M13/15