公开(公告)号：JP2002333465A

公开(公告)日：2002-11-22

申请号：JP2002060535

申请日：2002-03-06

Applicant: IBM

Inventor： WAGNER ISRAEL ,  GALAMBOS TIBI

IPC: G01R31/316 ,  G01R31/28 ,  G01R31/3167 ,  G01R31/3177 ,  G01R31/3183 ,  G06F17/10 ,  G06F17/18 ,  H03M1/10 ,  H03M1/12

Abstract: PROBLEM TO BE SOLVED: To conduct very high-speed histogram measurement on an analog integrated circuit component without requiring an analog test signal generating circuit on a chip. SOLUTION: A circuit mechanism for generating a histogram of output codes generated by an analog/digital converter (ADC) on the integrated circuit chip includes a comparator arranged on the chip together with the ADC. The first input of the comparator is connected to receive the output code from the ADC, and the second input is connected to receive a series of target codes including at least all the one portion of the output codes in one range. A pulse generator is arranged on the chip together with the ADC and the comparator to generate a pulse for an output from the chip based on a pulse rate determined by a clock signal of the ADC when an output of the comparator is received and when the output is under the first condition, and is connected thereto.

公开(公告)号：IL144430A

公开(公告)日：2005-05-17

申请号：IL14443001

申请日：2001-07-18

Applicant: IBM

Inventor： ZELIKSON MICHAEL ,  LEIBOWITZ MOSHE ,  WAGNER ISRAEL

IPC: H01L23/66 ,  H01R23/68