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    Weighted random pattern testing method.
    1.
    发明公开
    Weighted random pattern testing method. 失效
    Prüfverfahrenmittels gewichteten Zufallsmustergenerators。

    公开(公告)号：EP0206287A2

    公开(公告)日：1986-12-30

    申请号：EP86108463

    申请日：1986-06-20

    Applicant: IBM

    Inventor： MOTIKA FRANCO ,  WAICUKAUSKI JOHN ARTHUR

    IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50

    CPC classification number: G01R31/318385 ,  G01R31/31813 ,  G01R31/318371 ,  G01R31/318544

    Abstract: A method for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test (DUT), collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature (MISR = Multiple Input Signature Register) which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. … The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

    Abstract translation: 一种用于测试非常大规模的集成电路装置，特别是水平敏感扫描设计（LSSD）装置的方法，通过对被测设备（DUT）的每个输入端并行地应用不同配置的伪随机模式序列，收集 来自每个输出端子的输出响应并联，组合这些输出以获得作为所有并行输出序列的预定函数的签名（MISR =多输入签名寄存器），并将测试签名与已知的良好签名进行比较 通过计算机模拟获得。 ...输入测试刺激以预定方式进一步改变为待测试设备的结构的函数，以单独加权输入以有利于更多或更少的二进制或零。

    5.
    发明专利
    未知

    公开(公告)号：DE69209404T2

    公开(公告)日：1996-10-10

    申请号：DE69209404

    申请日：1992-07-18

    Applicant: IBM

    Inventor： KOENEMANN BERND KARL FERDINAND ,  WAGNER KENNETH DAVID ,  WAICUKAUSKI JOHN ARTHUR

    IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G06F11/27 ,  G06F11/26

    Abstract: A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.

    6.
    发明专利
    未知

    公开(公告)号：DE69209404D1

    公开(公告)日：1996-05-02

    申请号：DE69209404

    申请日：1992-07-18

    Applicant: IBM

    Inventor： KOENEMANN BERND KARL FERDINAND ,  WAGNER KENNETH DAVID ,  WAICUKAUSKI JOHN ARTHUR

    IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G06F11/27 ,  G06F11/26

    Abstract: A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.

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