公开(公告)号：JPS63175514A

公开(公告)日：1988-07-19

申请号：JP28861887

申请日：1987-11-17

Applicant: IBM

Inventor： BONNEAU MARTINE ,  BOUDON GERARD ,  LE GARREC JEAN-CLAUDE ,  MOLLIER PIERRE ,  WALLART FRANK

IPC: H03K3/3562 ,  H03K3/356

公开(公告)号：DE3684478D1

公开(公告)日：1992-04-23

申请号：DE3684478

申请日：1986-12-30

Applicant: IBM

Inventor： BONNEAU MARTINE ,  LE GARREC JEAN-CLAUDE ,  WALLART FRANK ,  BOUDON GERARD ,  MOLLIER PIERRE

IPC: H03K3/3562 ,  H03K3/356

Abstract: Disymmetry is produced in the DC mode by increased pmpedance connected in series with the second stage of the latch cell. The series impedances (R31,R32) are connected in the path for parasitic currents between the positive voltage source (Vdd) and earth (Gnd). When the data input (Do) is at logic one, the path to earth from the voltage source of parasitic current is through the first series resistance (R31) and transistor devices (P36,N33,N32). The first series resistance is embodied as a P-type transistor device (P38) of which the gate is earthed.