公开(公告)号：DE3478262D1

公开(公告)日：1989-06-22

申请号：DE3478262

申请日：1984-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： BLACHERE JEAN-MARIE ,  BONNEAU MARTINE ,  HORNUNG ROBERT

IPC: H01L21/822 ,  H01L21/82 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H01L27/10 ,  H01L23/52

公开(公告)号：JPS63175514A

公开(公告)日：1988-07-19

申请号：JP28861887

申请日：1987-11-17

Applicant: IBM

Inventor： BONNEAU MARTINE ,  BOUDON GERARD ,  LE GARREC JEAN-CLAUDE ,  MOLLIER PIERRE ,  WALLART FRANK

IPC: H03K3/3562 ,  H03K3/356

公开(公告)号：DE3684478D1

公开(公告)日：1992-04-23

申请号：DE3684478

申请日：1986-12-30

Applicant: IBM

Inventor： BONNEAU MARTINE ,  LE GARREC JEAN-CLAUDE ,  WALLART FRANK ,  BOUDON GERARD ,  MOLLIER PIERRE

IPC: H03K3/3562 ,  H03K3/356

Abstract: Disymmetry is produced in the DC mode by increased pmpedance connected in series with the second stage of the latch cell. The series impedances (R31,R32) are connected in the path for parasitic currents between the positive voltage source (Vdd) and earth (Gnd). When the data input (Do) is at logic one, the path to earth from the voltage source of parasitic current is through the first series resistance (R31) and transistor devices (P36,N33,N32). The first series resistance is embodied as a P-type transistor device (P38) of which the gate is earthed.

公开(公告)号：DE68925897D1

公开(公告)日：1996-04-11

申请号：DE68925897

申请日：1989-04-28

Applicant: IBM

Inventor： BONNEAU MARTINE ,  ONG IENG ,  GOUZE ERIC ,  PICCINO JEAN-MARC ,  HORNUNG ROBERT

IPC: H01L21/82 ,  H01L27/118

Abstract: A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, ...) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g. CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one large PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, ...) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.

公开(公告)号：DE68925897T2

公开(公告)日：1996-10-02

申请号：DE68925897

申请日：1989-04-28

Applicant: IBM

Inventor： BONNEAU MARTINE ,  ONG IENG ,  GOUZE ERIC ,  PICCINO JEAN-MARC ,  HORNUNG ROBERT

IPC: H01L21/82 ,  H01L27/118

Abstract: A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, ...) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g. CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one large PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, ...) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.