公开(公告)号：GB2511972A

公开(公告)日：2014-09-17

申请号：GB201410749

申请日：2012-11-07

Applicant: IBM

Inventor： BROWN JEFFREY D ,  COMPARAN MIGUEL ,  SHEARER ROBERT A ,  WATSON ALFRED T III

IPC: G01R31/3187 ,  G01R31/3183 ,  G01R31/3185 ,  G06F9/45 ,  G06F11/263 ,  G06F11/27

Abstract: IEE120067PCT ˉ40ˉ Abstract of the Disclosure A method and circuit arrangement utilize scan logic disposed on a multi- core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.