公开(公告)号：JPH10293782A

公开(公告)日：1998-11-04

申请号：JP4918098

申请日：1998-03-02

Applicant: IBM

Inventor： WIN K RUK ,  WEI FAN ,  KATAYAMA YASUNAO

IPC: H01L27/04 ,  G06F17/50 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To perform compilation to integrated logic and a DRAM system on a single chip from the hardware description language and wiring description of design composed of a DRAM macro and a logic macro by integrating logic and a DRAM memory to the same chip. SOLUTION: From a single processor memory chip for which a processor 21 is connected to a DRAM 22 by on-chip mutual connection 23, off-chip mutual connection disappears. Thus, by DRAM I/O and internal control, a memory data transfer rate utilizable for the processor 21 is raised for many digits. By integrating the processor 21 and the DRAM 22 to the same chip, the length of the on-chip mutual connection 23 and a capacitive load are substantially reduced and optimization is performed further by making the length of a wire shortest. As a result, a system clock speed is accelerated further and performance is improved.