公开(公告)号：JP2003030987A

公开(公告)日：2003-01-31

申请号：JP2002142731

申请日：2002-05-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK ,  STEPHENS JEREMY K ,  KIRIHATA TOSHIAKI

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C11/4091

Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture, in which coupling noise between bit lines is small at CMOS intersection coupling sensing operation, and which operates at a high speed.
SOLUTION: In a single bit-line direct sensing architecture, a sense amplifier circuit, having four transistors arranged for each memory array, is used. In this circuit, the transistor functions so that a data bit from a true bit-line of a pair of bit line or an auxiliary bit line is transferred selective to a data line. The data line is preferably arranged on a plurality of memory arrays, and the data line may not be required, to share in read operation and write operation. Furthermore, digital sensing scheme function is performed, by charging a data line during read-out operation using one more current source detecting the ratio of a current source, driving by a bit line of a corresponding array and resistance of a transistor.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种存储架构，其中位线之间的耦合噪声在CMOS交叉耦合感测操作处较小，并且以高速运行。 解决方案：在单个位线直接感测架构中，使用具有为每个存储器阵列布置的四个晶体管的读出放大器电路。 在该电路中，晶体管起作用，使得来自一对位线或辅助位线的真位置的数据位被选择性地传送到数据线。 数据线优选地布置在多个存储器阵列上，并且可能不需要数据线，以共享读操作和写操作。 此外，通过使用检测电流源的比例的一个电流源，通过相应阵列的位线驱动和晶体管的电阻来驱动读出操作期间的数据线，执行数字感测方案功能。

公开(公告)号：JP2003037491A

公开(公告)日：2003-02-07

申请号：JP2002136924

申请日：2002-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK

IPC: H03K19/0175 ,  G11C7/06 ,  G11C11/409 ,  H03K19/0944

CPC classification number: G11C7/04 ,  G11C7/067

Abstract: PROBLEM TO BE SOLVED: To provide a stabilized direct sensing memory architecture which provides Process, Voltage and Temperature(PVT) compensation in a memory array to a direct sense circuit to increase the manufacturing yield thereof, and to extend the operating voltage and temperature ranges thereof independent of manufacturing tolerances. SOLUTION: A single-ended sense amplifier structure has a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal, superimposed on a bitline precharge voltage. A simulating bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.

Abstract translation: 要解决的问题：提供一种稳定的直接感测存储器架构，其将存储器阵列中的过程，电压和温度（PVT）补偿提供给直接感测电路以增加其制造产量，并且延长其工作电压和温度范围 独立于制造公差。 解决方案：单端读出放大器结构具有公共源极NFET放大器，具有由PFET提供的可调电流源负载。 自动调节PFET电流源，使NFET放大器工作在一个工作范围内，以提供叠加在位线预充电电压上的小信号的最大放大。 模拟偏置发生器电路提供该工作点调整，并且使用少量晶体管实现直接的单端感测操作。

公开(公告)号：JPH10293782A

公开(公告)日：1998-11-04

申请号：JP4918098

申请日：1998-03-02

Applicant: IBM

Inventor： WIN K RUK ,  WEI FAN ,  KATAYAMA YASUNAO

IPC: H01L27/04 ,  G06F17/50 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To perform compilation to integrated logic and a DRAM system on a single chip from the hardware description language and wiring description of design composed of a DRAM macro and a logic macro by integrating logic and a DRAM memory to the same chip. SOLUTION: From a single processor memory chip for which a processor 21 is connected to a DRAM 22 by on-chip mutual connection 23, off-chip mutual connection disappears. Thus, by DRAM I/O and internal control, a memory data transfer rate utilizable for the processor 21 is raised for many digits. By integrating the processor 21 and the DRAM 22 to the same chip, the length of the on-chip mutual connection 23 and a capacitive load are substantially reduced and optimization is performed further by making the length of a wire shortest. As a result, a system clock speed is accelerated further and performance is improved.