4F- SQUARE MEMORY CELL HAVING VERTICAL FLOATING- GATE TRANSISTORS WITH SELF- ALIGNED SHALLOW TRENCH ISOLATION

    公开(公告)号:MY126393A

    公开(公告)日:2006-09-29

    申请号:MYPI9706119

    申请日:1997-12-18

    Applicant: IBM

    Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE ARRAY HAS COLUMNS OF BITLINES (220, 700, 705) AND ROWS OF WORDLINES (225, 225'). THE GATES (275, 275') OF THE TRANSISTORS ACT AS THE WORDLINES, WHILE THE SOURCE OR DRAIN REGIONS (215, 240, 405, 755, 774) ACTS AS THE BITLINES. THE ARRAY ALSO HAS VERTICAL PILLARS (230), ACTING AS A CHANNEL, FORMED BETWEEN SOURCE AND DRAIN REGIONS. THE SOURCE REGIONS ARE SELF-ALIGNED AND LOCATED BELOW THE PILLARS. THE SOURCE REGIONS OF ADJACENT BITLINES ARE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED.THE ISOLATED SOURCES ALLOW INDIVIDUAL CELLS (205, 400, 545) TO BE ADDRESSED AND WRITTEN VIA DIRECT TUNNELING, IN BOTH VOLATILE AND NON-VOLATILE MEMORY CELL CONFIGURATIONS. THE SOURCE MAY BE INITIALLY IMPLANTED. ALTERNATIVELY, THE SOURCE MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE SOURCE DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE (235), OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE.(FIG 8)

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