公开(公告)号：DE69626562D1

公开(公告)日：2003-04-17

申请号：DE69626562

申请日：1996-04-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： ECKSTEIN ELKE ,  HOFFMAN BIRGIT ,  KIEWRA EDWARD W ,  KOCON WALDEMAR WALTER ,  WEISS MARK JAY

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/321 ,  H01L21/311

Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.

公开(公告)号：SG60174A1

公开(公告)日：1999-02-22

申请号：SG1997004574

申请日：1997-12-19

Applicant: IBM

Inventor： BURNS STUART MCALLISTER JR ,  HANAEL HUSSEIN IBRAHIM ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/105

Abstract: A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof. In this case, the source diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

公开(公告)号：DE69626562T2

公开(公告)日：2004-02-19

申请号：DE69626562

申请日：1996-04-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： ECKSTEIN ELKE ,  HOFFMAN BIRGIT ,  KIEWRA EDWARD W ,  KOCON WALDEMAR WALTER ,  WEISS MARK JAY

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/321 ,  H01L21/311

Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.

公开(公告)号：SG66418A1

公开(公告)日：1999-07-20

申请号：SG1997004440

申请日：1997-12-15

Applicant: IBM

Inventor： BURNS STUART MCALLISTER JR ,  HANAEL HUSSEIN IBRAHIM ,  KALTER HOWAR LEO ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

IPC: H01L21/24 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/8247 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

Abstract: A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of all the cells are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The array is suitable for Gbit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

公开(公告)号：MY126393A

公开(公告)日：2006-09-29

申请号：MYPI9706119

申请日：1997-12-18

Applicant: IBM

Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM ,  KOCON WALDEMAR WALTER ,  WELSER JEFFERY J

IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE ARRAY HAS COLUMNS OF BITLINES (220, 700, 705) AND ROWS OF WORDLINES (225, 225'). THE GATES (275, 275') OF THE TRANSISTORS ACT AS THE WORDLINES, WHILE THE SOURCE OR DRAIN REGIONS (215, 240, 405, 755, 774) ACTS AS THE BITLINES. THE ARRAY ALSO HAS VERTICAL PILLARS (230), ACTING AS A CHANNEL, FORMED BETWEEN SOURCE AND DRAIN REGIONS. THE SOURCE REGIONS ARE SELF-ALIGNED AND LOCATED BELOW THE PILLARS. THE SOURCE REGIONS OF ADJACENT BITLINES ARE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED.THE ISOLATED SOURCES ALLOW INDIVIDUAL CELLS (205, 400, 545) TO BE ADDRESSED AND WRITTEN VIA DIRECT TUNNELING, IN BOTH VOLATILE AND NON-VOLATILE MEMORY CELL CONFIGURATIONS. THE SOURCE MAY BE INITIALLY IMPLANTED. ALTERNATIVELY, THE SOURCE MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE SOURCE DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE (235), OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE.(FIG 8)

公开(公告)号：MY118306A

公开(公告)日：2004-09-30

申请号：MYPI9706162

申请日：1997-12-18

Applicant: IBM

Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM ,  KALTER HOWARD LEO ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES, HAVING PILLARS (230) WITH STACK CAPACITORS (520, 520'') THEREON, AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE PILLARS ACT AS TRANSISTOR CHANNELS, AND ARE FORMED BETWEEN UPPER AND LOWER DOPED REGIONS (240, 405). THE LOWER DOPED REGIONS ARE SELF-ALIGNED AND ARE LOCATED BELOW THE PILLARS. THE ARRAY HAS COLUMNS OF BITLINES (220,700, 705) AND ROWS OF WORD LINES (225, 225''). THE LOWER DOPED REGIONS OF ADJACENT BITLINES MAY BE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED. THE ARRAY IS SUITABLE FOR GBIT DRAM APPLICATIONS BECAUSE THE STACK CAPACITORS DO NOT INCREASE ARRAY AREA. THE ARRAY MAY HAVE AN OPEN BITLINE, A FOLDED, OR AN OPEN/FOLDED ARCHITECTURE WITH DUAL WORDLINES, WHERE TWO TRANSISTORS ARE FORMED ON TOP OF EACH OTHER IN EACH TRENCH. THE LOWER REGIONS MAY BE INITIALLY IMPLANTED. ALTERNATIVE1Y, THE LOWER REGIONS MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE LOWER REGION DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE, OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE. (FIG.8)

公开(公告)号：AT234508T

公开(公告)日：2003-03-15

申请号：AT96105741

申请日：1996-04-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： ECKSTEIN ELKE ,  HOFFMAN BIRGIT ,  KIEWRA EDWARD W ,  KOCON WALDEMAR WALTER ,  WEISS MARK JAY

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/321 ,  H01L21/311

Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.