公开(公告)号：DE2926094A1

公开(公告)日：1981-01-08

申请号：DE2926094

申请日：1979-06-28

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  WIEDMANN SIEGFRIED DR ING

IPC: G11C11/414 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/4063 ,  G11C11/411 ,  G11C11/416

Abstract: A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.

公开(公告)号：DE2960919D1

公开(公告)日：1981-12-17

申请号：DE2960919

申请日：1979-03-16

Applicant: IBM

Inventor： HEUBER KLAUS DIPL ING ,  KLINK ERICH DIPL ING ,  RUDOLPH VOLKER DIPL PHYS ,  WIEDMANN SIEGFRIED DR ING

IPC: G11C11/40 ,  G11C11/411 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/08 ,  H01L27/082 ,  H01L29/73 ,  H03K3/288 ,  H03K19/091

Abstract: The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I2L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I2L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I2L structures each which are cross-coupled in the manner of a flip-flop.