中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.033 seconds)

    PHASE SPLITTER WITH INTEGRATED LATCHING CIRCUIT
    1.
    发明专利
    PHASE SPLITTER WITH INTEGRATED LATCHING CIRCUIT 未知

    公开(公告)号：DE3268802D1

    公开(公告)日：1986-03-13

    申请号：DE3268802

    申请日：1982-07-13

    Applicant: IBM DEUTSCHLAND ,  IBM

    Inventor： KLEIN WILFRIED DIPL ING ,  KLINK ERICH DIPL ING ,  NAJMANN KNUT DIPL ING ,  WERNICKE FRIEDRICH DIPL ING

    IPC: H03K3/286 ,  H03K3/287 ,  H03K19/20

    Abstract: Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the previously set switching state or of the output signals, respectively, and where a simple clocking for functional control can be used. The advantages presented by the disclosed Phase splitter substantially consist in that the speed with which the complementary output signals are supplied is extremely high since the output signals are available directly, i.e. with only one stage delay, the latch circuit being non-conductive in the stationary state, and thus in a latching process does not have to be switched from one stage to the other, but only switched on.

    LATCHED PHASE SPLITTER
    2.
    发明专利
    LATCHED PHASE SPLITTER 未知

    公开(公告)号：DE3371960D1

    公开(公告)日：1987-07-09

    申请号：DE3371960

    申请日：1983-08-17

    Applicant: IBM DEUTSCHLAND ,  IBM

    Inventor： BROSCH RUDOLF DR ING ,  KEINERT JOACHIM ,  KLINK ERICH DIPL ING ,  WERNICKE FRIEDRICH C DIPL ING

    IPC: H03K3/286 ,  H03K3/288 ,  H03K5/02 ,  H03K5/151

    Abstract: A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transitor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.

    4.
    发明专利
    未知

    公开(公告)号：DE68905475D1

    公开(公告)日：1993-04-22

    申请号：DE68905475

    申请日：1989-07-18

    Applicant: IBM

    Inventor： KLINK ERICH DIPL ING ,  KOHLER HELMUT DIPL ING ,  PROSS HARALD DIPL ING

    IPC: H01L23/50 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065

    Abstract: A method and a memory module are provided which allow the duplication of the density of a memory module with a minimum of increasing of the module size and with low manufacturing costs. The method uses well-known techniques which are used by the manufacturing of DIP modules containing only one chip inside the moulded plastic or ceramic housing. Contrary to with the common methods the inner bond leads are punched so that they have a greater width than the common inner bond leads. Subsequently or together with the punching step the inner bond leads are slotted in order to allow the bending of at least one of each of the smaller inner bond leads obtained before for providing a space between the two inner bond leads. Next, two semiconductor memory chips are glued together back-to-back and inserted in the gap between the upper inner bond leads and the lower inner bond leads so that the upper and lower bond leads embrace the two chips. The chips can be equal with the pad occupation, or mirrored. The method is applicable to dual inline package (DIP) as well as to ZIG-ZAG package. The semiconductor memory module comprises a housing (4) of plastic or ceramic in which two chips (8, 10) are stacked together back-to-back. The pads (20) of the chips are electrically connected by wire-bonding to beam leads (14) which comprise outer bond leads (6), generally arranged outside the housing to form the ocntact pins or contact leads of the module to a printed circuit board, and inner bond leads (16) in the housing. The inner bond leads are spread in the area of the inner lead bond ends into upper (16a) and lower (16b) bond leads forming a gap (22) for receiving and embracing the stacked chips.

    6.
    发明专利
    未知

    公开(公告)号：DE68905475T2

    公开(公告)日：1993-09-16

    申请号：DE68905475

    申请日：1989-07-18

    Applicant: IBM

    Inventor： KLINK ERICH DIPL ING ,  KOHLER HELMUT DIPL ING ,  PROSS HARALD DIPL ING

    IPC: H01L23/50 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065

    Abstract: A method and a memory module are provided which allow the duplication of the density of a memory module with a minimum of increasing of the module size and with low manufacturing costs. The method uses well-known techniques which are used by the manufacturing of DIP modules containing only one chip inside the moulded plastic or ceramic housing. Contrary to with the common methods the inner bond leads are punched so that they have a greater width than the common inner bond leads. Subsequently or together with the punching step the inner bond leads are slotted in order to allow the bending of at least one of each of the smaller inner bond leads obtained before for providing a space between the two inner bond leads. Next, two semiconductor memory chips are glued together back-to-back and inserted in the gap between the upper inner bond leads and the lower inner bond leads so that the upper and lower bond leads embrace the two chips. The chips can be equal with the pad occupation, or mirrored. The method is applicable to dual inline package (DIP) as well as to ZIG-ZAG package. The semiconductor memory module comprises a housing (4) of plastic or ceramic in which two chips (8, 10) are stacked together back-to-back. The pads (20) of the chips are electrically connected by wire-bonding to beam leads (14) which comprise outer bond leads (6), generally arranged outside the housing to form the ocntact pins or contact leads of the module to a printed circuit board, and inner bond leads (16) in the housing. The inner bond leads are spread in the area of the inner lead bond ends into upper (16a) and lower (16b) bond leads forming a gap (22) for receiving and embracing the stacked chips.

    7.
    发明专利
    未知

    公开(公告)号：DE2816949A1

    公开(公告)日：1979-10-25

    申请号：DE2816949

    申请日：1978-04-19

    Applicant: IBM DEUTSCHLAND

    Inventor： HEUBER KLAUS DIPL ING ,  KLINK ERICH DIPL ING ,  RUDOLPH VOLKER DIPL PHYS DR ,  WIEDMANN SIEGFRIED KURT DIPL I

    IPC: G11C11/40 ,  G11C11/411 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/08 ,  H01L27/082 ,  H01L29/73 ,  H03K3/288 ,  H03K19/091 ,  H01L27/04

    Abstract: The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I2L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I2L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I2L structures each which are cross-coupled in the manner of a flip-flop.

Patent Agency Ranking