公开(公告)号：DE2960919D1

公开(公告)日：1981-12-17

申请号：DE2960919

申请日：1979-03-16

Applicant: IBM

Inventor： HEUBER KLAUS DIPL ING ,  KLINK ERICH DIPL ING ,  RUDOLPH VOLKER DIPL PHYS ,  WIEDMANN SIEGFRIED DR ING

IPC: G11C11/40 ,  G11C11/411 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/08 ,  H01L27/082 ,  H01L29/73 ,  H03K3/288 ,  H03K19/091

Abstract: The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I2L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I2L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I2L structures each which are cross-coupled in the manner of a flip-flop.

公开(公告)号：DE2926094A1

公开(公告)日：1981-01-08

申请号：DE2926094

申请日：1979-06-28

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  WIEDMANN SIEGFRIED DR ING

IPC: G11C11/414 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/4063 ,  G11C11/411 ,  G11C11/416

Abstract: A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.

公开(公告)号：DE2556833A1

公开(公告)日：1977-06-30

申请号：DE2556833

申请日：1975-12-17

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL ING ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40 ,  H01L29/76

Abstract: An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

公开(公告)号：DE2511518A1

公开(公告)日：1976-09-16

申请号：DE2511518

申请日：1975-03-15

Applicant: IBM DEUTSCHLAND

Inventor： BERGER HORST DIPL ING DR ,  HEUBER KLAUS DIPL ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL ING ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/416 ,  G11C7/00 ,  G11C11/40

Abstract: The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.

公开(公告)号：DE2855866A1

公开(公告)日：1980-06-26

申请号：DE2855866

申请日：1978-12-22

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  H01L27/02 ,  G11C7/00

公开(公告)号：DE2816949A1

公开(公告)日：1979-10-25

申请号：DE2816949

申请日：1978-04-19

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  KLINK ERICH DIPL ING ,  RUDOLPH VOLKER DIPL PHYS DR ,  WIEDMANN SIEGFRIED KURT DIPL I

IPC: G11C11/40 ,  G11C11/411 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/08 ,  H01L27/082 ,  H01L29/73 ,  H03K3/288 ,  H03K19/091 ,  H01L27/04

Abstract: The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I2L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I2L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance. The invention further relates to a storage arrangement having storage cells including two such I2L structures each which are cross-coupled in the manner of a flip-flop.

公开(公告)号：DE2514466A1

公开(公告)日：1976-10-14

申请号：DE2514466

申请日：1975-04-03

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  NAJMANN KNUT DIPL ING ,  REMSHARDT ROLF DIPL ING DR ,  TERTEL KLAUS

IPC: H01L21/822 ,  H01L21/761 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06

公开(公告)号：DE2460146A1

公开(公告)日：1976-06-24

申请号：DE2460146

申请日：1974-12-19

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL ING ,  REMSHARDT ROLF DIPL ING DR ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/416 ,  H03K3/287 ,  H03K5/02 ,  G11C7/00 ,  G11C11/40

Abstract: This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.