公开(公告)号：JP2008306204A

公开(公告)日：2008-12-18

申请号：JP2008199617

申请日：2008-08-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MARK C HEIKEE ,  HOLMES STEVEN J ,  DAVID V HOLICK ,  WILLIAM H MA

IPC: G03F7/004 ,  H01L21/8242 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/02 ,  H01L21/027 ,  H01L21/308 ,  H01L27/108

CPC classification number: H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085 ,  Y10S430/168 ,  Y10T428/24355 ,  Y10T428/24628

Abstract: PROBLEM TO BE SOLVED: To provide an easy method for manufacturing a high capacitance storage node structure for DRAM, and the like. SOLUTION: A high-capacitance storage node structure is produced in a substrate 10, by patterning a hybrid resist 12, to produce both negative tone resist regions 16 and positive tone resist regions 18 in the exposed region 14. After the removal of the positive tone resist regions 18, the substrate 10 is etched by using the unexposed hybrid resist 12 and negative tone resist regions 16 as a mask. This produces a trench 22 in the substrate 10 with a centrally located, upwardly projecting protrusion 24. A capacitor 26 is then produced by coating the sidewalls of the trench 22 and protrusion 24 with a dielectric 28 and filling the trench 22 with a conductive material 30, such as polysilicon. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供用于制造用于DRAM的高电容存储节点结构的简单方法等。 解决方案：通过图案化混合抗蚀剂12，在衬底10中产生高电容存储节点结构，以在暴露区域14中产生负色调抗蚀剂区域16和正色调抗蚀剂区域18。 通过使用未曝光的混合抗蚀剂12和负色调抗蚀剂区域16作为掩模来蚀刻正色调抗蚀剂区域18，衬底10。 这在基板10中产生具有中心定位的向上突出的突起24的沟槽22.然后通过用电介质28涂覆沟槽22和突起24的侧壁并用导电材料30填充沟槽22来产生电容器26 ，如多晶硅。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH11274478A

公开(公告)日：1999-10-08

申请号：JP2893699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  WILLIAM H MA ,  MANDELMAN JACK A

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2255 ,  H01L29/66621 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element reducing a short channel effect. SOLUTION: An element has a trench 370 formed in a silicon substrate 305. The channel 380 of the element is formed on the bottom portion of the trench 370. Diffusion layers 310, 320 are formed adjacently to both sides of the trench 370 and are extended along the side walls of the trench 370 and under a part of the trench 370 to form diffusion extension parts 315, 325, whereby each diffusion layer is connected to each edge of the element channel.

Abstract translation: 要解决的问题：提供减少短通道效应的半导体元件。 解决方案：元件具有形成在硅衬底305中的沟槽370.元件的沟道380形成在沟槽370的底部上。扩散层310,320形成在沟槽370的两侧相邻并且延伸 沿着沟槽370的侧壁并在沟槽370的一部分之下形成扩散延伸部分315,325，由此每个扩散层连接到元件沟道的每个边缘。

公开(公告)号：JPH10154796A

公开(公告)日：1998-06-09

申请号：JP25115797

申请日：1997-09-16

Applicant: IBM

Inventor： MARK C HEIKEE ,  STEPHEN J HORMES ,  DAVID V HOLICK ,  WILLIAM H MA

IPC: G03F7/038 ,  G03F7/039 ,  G03F7/26 ,  G03F7/40 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30.