公开(公告)号：JPH1174197A

公开(公告)日：1999-03-16

申请号：JP19292198

申请日：1998-07-08

Applicant: IBM

Inventor： JAMES A BRUCE ,  STEPHEN J HORMES ,  LEIDY ROBERT K ,  MLYNKO WALTER E ,  EDWARD W SENGL

IPC: G03F7/004 ,  G03F1/00 ,  G03F7/095 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To enable regions to be demarcated through a single masking step by a method, wherein a hybrid resist is irradiated with an actinic radiation energy to expose a first region on a mask, and a second region is exposed on the mask by uniform exposure. SOLUTION: An oxide layer and a nitride layer are formed on a wafer, and a hybrid resist layer is attached, exposed to light through a mask, and developed to form a space (302 to 308). The nitride layer is etched through the space (310), uniform exposure and development are carried out (312), and silicon is etched to the hybrid resist and the nitride layer to form an STI region (314). Then, the exposed nitride and the oxide are removed, a silicon dioxide layer is attached to an unblocked silicon, the nitride is etched (316 to 322), a nitride spacer is formed in an edge STI region, silicon dioxide is attached, a wafer is planarized and the residual nitride and the oxide are removed (324 to 330).

公开(公告)号：JPH1174196A

公开(公告)日：1999-03-16

申请号：JP19275998

申请日：1998-07-08

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  KAKU K HYUIN ,  LEIDY ROBERT K ,  PAUL W PASTELL

IPC: H01L29/78 ,  G03F7/095 ,  G03F7/38 ,  H01L21/027 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To enable junctions of a gate/source and a gate/drain to be enhanced in control in doping by a method, wherein a side wall spacer trough is demarcated by the use of a hybrid resist. SOLUTION: A wafer is prepared, and a hybrid resist layer is attached to the wafer, exposed to light through a mask, and developed (302 to 308) for the formation of a sidewall spacer. A hard mask is etched through a spacer (301), a uniform exposure process and a development process are carried out (312), a gate matter is etched through the residual hard mask (314), and a sidewall spacer trough is formed. Then, the exposed hard mask and a negative-type hybrid resist are removed (316 and 313), and a gate edge implant is formed (320). Then, a sidewall oxide and a nitride stopper are attached (322), an excess sidewall spacer matter and an excess gate matter are removed (326 and 328), and are injected (330) to a source and a drain region.

公开(公告)号：JPH11330384A

公开(公告)日：1999-11-30

申请号：JP20197998

申请日：1998-07-16

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  LEIDY ROBERT K ,  STEPHEN H BALDEMAN

IPC: G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  H01L21/336 ,  H01L27/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enhance a CMOS device in latch up resistance, by a method wherein a side wall spacer/trough region is demarcated and formed by the use of hybrid photoresist which shows a positive-type, a negative type and an intermediate-type reaction to exposure light. SOLUTION: A gate oxide layer 2404 and a gate material layer 2406 are successively deposited on a wafer 2500, and side wall spacer troughs 2801 and 2802 are provided to the gate oxide layer 2404 and the gate material layer 2406 by the use of hybrid photoresist which shows a positive-type, a negative- type, and an intermediate-type reaction to exposure light. Three regions, a gate region 2804, a high source region 2806, and a high drain region 2808 are provided to the side wall spacer troughs 2801 and 2802, and a residual negative- type pattern 2526 and a residual hard mask layer 2408 are formed. By this setup, a CMOS device can be improved in latch-up resistance.

公开(公告)号：JPH11274478A

公开(公告)日：1999-10-08

申请号：JP2893699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  WILLIAM H MA ,  MANDELMAN JACK A

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2255 ,  H01L29/66621 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element reducing a short channel effect. SOLUTION: An element has a trench 370 formed in a silicon substrate 305. The channel 380 of the element is formed on the bottom portion of the trench 370. Diffusion layers 310, 320 are formed adjacently to both sides of the trench 370 and are extended along the side walls of the trench 370 and under a part of the trench 370 to form diffusion extension parts 315, 325, whereby each diffusion layer is connected to each edge of the element channel.

Abstract translation: 要解决的问题：提供减少短通道效应的半导体元件。 解决方案：元件具有形成在硅衬底305中的沟槽370.元件的沟道380形成在沟槽370的底部上。扩散层310,320形成在沟槽370的两侧相邻并且延伸 沿着沟槽370的侧壁并在沟槽370的一部分之下形成扩散延伸部分315,325，由此每个扩散层连接到元件沟道的每个边缘。

公开(公告)号：JPH10335486A

公开(公告)日：1998-12-18

申请号：JP12100598

申请日：1998-04-30

Applicant: IBM

Inventor： JEFFREY S BROWN ,  STEPHEN J HORMES ,  LEIDY ROBERT K ,  VOLDMAN STEVEN H

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866

Abstract: PROBLEM TO BE SOLVED: To form a buried Zener diode having a sufficiently low breakdown voltage level, by generating a self-aligning Zener diode by executing a two-state photography mask process in a hybrid photoresist process. SOLUTION: A positive line pattern is formed on an N-well area, and a negative line pattern is formed on the other area than the N-well area. After N-well sedge implant 2302 is formed, the positive line pattern is removed and an N-well 2402 is formed. Then, a positive line pattern 2510 is formed on a p-well area and a negative line pattern 2508 is formed on the other area than the P-well area. Thereafter, an embedded Zener diode is formed by forming P-well edge implant 2602. Therefore, the number of required process masks can be reduced and the alignment problem of the photolightography can be reduced.

公开(公告)号：JPH10321807A

公开(公告)日：1998-12-04

申请号：JP12094798

申请日：1998-04-30

Applicant: IBM

Inventor： FEI D BAKER ,  JEFFREY S BROWN ,  ROBERT J GAUZAR ,  STEPHEN J HORMES ,  ROBERT K LADY ,  EDWARD J NOWACK ,  VOLDMAN STEVEN H

IPC: H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To improve the latch-up resistance of a CMOS device by forming implants on the edges of an N well and/or a P well by using a hybrid resist and, at the same time, to improve the device density of the CMOS device by promoting the scaling of the device. SOLUTION: A wafer section 2100 can be completed by an appropriate manufacturing method, for example, by forming a device gate, a contact diffusion area, etc. In the wafer section 2100, in addition, N and P contact diffusion areas are formed. In these contact diffusion areas, implants are usually formed on the surface of silicon which is not masked with a polysilicon gate. Therefore, a method and a structure for reducing the latch-up of a CMOS device by forming N and/or P edge implants on the edges of a P-well, N-well, and/or a double well are obtained.

公开(公告)号：JPH10154796A

公开(公告)日：1998-06-09

申请号：JP25115797

申请日：1997-09-16

Applicant: IBM

Inventor： MARK C HEIKEE ,  STEPHEN J HORMES ,  DAVID V HOLICK ,  WILLIAM H MA

IPC: G03F7/038 ,  G03F7/039 ,  G03F7/26 ,  G03F7/40 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30.