公开(公告)号：JP2008306204A

公开(公告)日：2008-12-18

申请号：JP2008199617

申请日：2008-08-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MARK C HEIKEE ,  HOLMES STEVEN J ,  DAVID V HOLICK ,  WILLIAM H MA

IPC: G03F7/004 ,  H01L21/8242 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/02 ,  H01L21/027 ,  H01L21/308 ,  H01L27/108

CPC classification number: H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085 ,  Y10S430/168 ,  Y10T428/24355 ,  Y10T428/24628

Abstract: PROBLEM TO BE SOLVED: To provide an easy method for manufacturing a high capacitance storage node structure for DRAM, and the like. SOLUTION: A high-capacitance storage node structure is produced in a substrate 10, by patterning a hybrid resist 12, to produce both negative tone resist regions 16 and positive tone resist regions 18 in the exposed region 14. After the removal of the positive tone resist regions 18, the substrate 10 is etched by using the unexposed hybrid resist 12 and negative tone resist regions 16 as a mask. This produces a trench 22 in the substrate 10 with a centrally located, upwardly projecting protrusion 24. A capacitor 26 is then produced by coating the sidewalls of the trench 22 and protrusion 24 with a dielectric 28 and filling the trench 22 with a conductive material 30, such as polysilicon. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供用于制造用于DRAM的高电容存储节点结构的简单方法等。 解决方案：通过图案化混合抗蚀剂12，在衬底10中产生高电容存储节点结构，以在暴露区域14中产生负色调抗蚀剂区域16和正色调抗蚀剂区域18。 通过使用未曝光的混合抗蚀剂12和负色调抗蚀剂区域16作为掩模来蚀刻正色调抗蚀剂区域18，衬底10。 这在基板10中产生具有中心定位的向上突出的突起24的沟槽22.然后通过用电介质28涂覆沟槽22和突起24的侧壁并用导电材料30填充沟槽22来产生电容器26 ，如多晶硅。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH10104834A

公开(公告)日：1998-04-24

申请号：JP22504197

申请日：1997-08-21

Applicant: IBM

Inventor： MARK C HEIKEE ,  STEVEN J HOLMES ,  DAVID V HAULICK ,  AHAMADO D KATONANI ,  NIRANJAN M PATEL ,  PAUL A LABIDACKS

IPC: G03F7/004 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/02 ,  H01L21/027 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To make it possible to extremely precisely control images with an image size as a target separate form the image size control on a reticle by constituting this regency doubling hybrid phutorsist by, having both of negative type response and positive type response and forming spaces in diffraction regions exposed with an intermediate quantity of irradiation energy. SOLUTION: This hybrid resist simultaneously has both responsiveness of the positive type and negative type to exposure. The solubility of the hybrid resist is increased in the regions, such as regions near the edges of the reticule images, where the exposure intensity is degraded by a diffraction effect by positive responsibility. When the irradiation quantity increases, the negative type responsiveness is dominant. Then, the solubility in the regions where the exposure is large degrades. When a substrate is printed with reticle line patterns, space/line/space patterns are obtd. The space images are 'frequency doubled' in such a manner, the features of double the case of a standard resist are formed. Such hybrid resist exhibits the patterns distinctly different from the positive type resist and the negative type resist.

公开(公告)号：JPH10154796A

公开(公告)日：1998-06-09

申请号：JP25115797

申请日：1997-09-16

Applicant: IBM

Inventor： MARK C HEIKEE ,  STEPHEN J HORMES ,  DAVID V HOLICK ,  WILLIAM H MA

IPC: G03F7/038 ,  G03F7/039 ,  G03F7/26 ,  G03F7/40 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30.