公开(公告)号：MY126847A

公开(公告)日：2006-10-31

申请号：MYPI20012434

申请日：2001-05-23

Applicant: IBM

Inventor： WILLIAM R TONTI ,  CLAUDE L BERTIN ,  RAMACHANDRA DIVAKARUNI ,  JACK A MANDELMAN ,  RUSSELL J HOUGHTON

IPC: H01L21/82 ,  H01L29/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI?FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON?ON?INSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR?LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI?FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR?LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION. HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF?REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED. (FIG. 6)

公开(公告)号：SG97819A1

公开(公告)日：2003-08-20

申请号：SG1999005478

申请日：1999-11-05

Applicant: IBM

Inventor： JOHN E BARTH ,  CLAUDE LOUIS BERTIN ,  JEFFREY H DREIBELBIS ,  WAYNE F ELLIS ,  WAYNE JOHN HOWELL ,  ERIK L HEDBERG ,  HOWARD L KALTER ,  WILLIAM R TONTI ,  DONALD L WHEATER

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/319 ,  H01L23/485

Abstract: Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.