公开(公告)号：MY126847A

公开(公告)日：2006-10-31

申请号：MYPI20012434

申请日：2001-05-23

Applicant: IBM

Inventor： WILLIAM R TONTI ,  CLAUDE L BERTIN ,  RAMACHANDRA DIVAKARUNI ,  JACK A MANDELMAN ,  RUSSELL J HOUGHTON

IPC: H01L21/82 ,  H01L29/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI?FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON?ON?INSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR?LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI?FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR?LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION. HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF?REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED. (FIG. 6)

公开(公告)号：MY116040A

公开(公告)日：2003-10-31

申请号：MYPI19993047

申请日：1999-07-20

Applicant: IBM

Inventor： FARIBORZ ASSADERAGHI ,  CLAUDE L BERTIN ,  JEFFREY P GAMBINO ,  LOUIS LU-CHEN HSU ,  JACK ALLAN MANDELMAN

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: AN ACTIVE FET BODY DEVICE WHICH COMPRISES AN ACTIVE FET REGION INCLUDING A GATE (13, 15, 16,24,26,28,30,3 I), A BODY REGION (4) AND ELECTRICAL CONNECTION BETWEEN SAID GATE AND SAID BODY REGION THAT IS LOCATED WITHIN THE ACTIVE FET REGION IS PROVIDED ALONG WITH VARIOUS METHODS FOR FABRICATING THE DEVICES. THE ELECTRICAL CONNECTION EXTENDS OVER SUBSTANTIALLY THE ENTIRE WIDTH OF THE FET. (FIGURE 6)