公开(公告)号：JP2007335860A

公开(公告)日：2007-12-27

申请号：JP2007150183

申请日：2007-06-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RADENS CARL JOHN ,  RAMACHANDRA DIVAKARUNI ,  CHENG KANGGUO

IPC: H01L21/822 ,  H01L27/04

CPC classification number: H01L29/945 ,  H01L29/66931

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and a method for forming the same. SOLUTION: The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体结构及其形成方法。 解决方案：半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：MY126847A

公开(公告)日：2006-10-31

申请号：MYPI20012434

申请日：2001-05-23

Applicant: IBM

Inventor： WILLIAM R TONTI ,  CLAUDE L BERTIN ,  RAMACHANDRA DIVAKARUNI ,  JACK A MANDELMAN ,  RUSSELL J HOUGHTON

IPC: H01L21/82 ,  H01L29/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI?FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON?ON?INSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR?LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI?FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR?LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION. HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF?REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED. (FIG. 6)

公开(公告)号：SG91923A1

公开(公告)日：2002-10-15

申请号：SG200102773

申请日：2001-05-10

Applicant: IBM

Inventor： CLAUDE LOUIS BERTIN ,  RAMACHANDRA DIVAKARUNI ,  RUSSELL J HOUGHTON ,  JACK ALLAN MANDELMAN ,  WILLIAM ROBERT PATRICK TONTI

IPC: H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L21/84

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

公开(公告)号：SG108827A1

公开(公告)日：2005-02-28

申请号：SG200106036

申请日：2001-10-01

Applicant: IBM

Inventor： JAMES W ADKISSON ,  RAMACHANDRA DIVAKARUNI ,  JEFFREY PETER GAMBINO ,  JACK ALLAN MANDELMAN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L23/538

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped glass to smooth the 250 nm step at the edge of the DRAM array region, making it easier to perform the lithography used to pattern the deep trenches (32) for storage in the bulk region. The resulting structure is also disclosed.

公开(公告)号：SG84601A1

公开(公告)日：2001-11-20

申请号：SG200002902

申请日：2000-05-26

Applicant: IBM

Inventor： JACK ALLAN MANDELMAN ,  GARY BELA BRONNER ,  RAMACHANDRA DIVAKARUNI

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/22

Abstract: A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.