公开(公告)号：CA1077604A

公开(公告)日：1980-05-13

申请号：CA267508

申请日：1976-12-09

Applicant: IBM

Inventor： DEBAR DAVID E ,  DE LA MONEDA FRANCISCO H

IPC: H01L21/66 ,  H01L21/82 ,  H01L27/146 ,  H01L31/08 ,  H01L31/18

Abstract: Variations of current gain from element to element in a phototransistor array are eliminated by covering the array with an opaque mask and etching openings in the mask over each phototransistor based upon an area reduction factor (ARF). The area reduction factor for an opening is equal to (Im/Ix)1-n where n is a constant definitive of the change in beta of a phototransistor in the array over a given range of collector currents; Im is the minimum collector current measured for the array and Ix is the collector current for the phototransistor beneath the opening. Based upon the ARF's, the openings etched in the mask or cover initiate uniform current form each phototransistor element when uniform light flux is directed on the array. The process of fabricating the array comprises measuring the collector current for each phototransistor element at a given uniform light flux; determining the element with minimum collector current in the array; calculating the ARF for each phototransistor to achieve a uniform current response from the array; coating the array with an opaque cover, and etching the cover at each phototransistor based upon the ARF.

公开(公告)号：DE3071925D1

公开(公告)日：1987-04-16

申请号：DE3071925

申请日：1980-11-10

Applicant: IBM

Inventor： KOTECHA HARISH N ,  DE LA MONEDA FRANCISCO H

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/00

Abstract: A DMOS field effect transistor device and fabrication process is disclosed whereby a precisely defined channel length is generated between a source region (44a) and a drain region (46a) of a second conductivity type within a substrate of a first conductivity type. … A first ion-implanted region (68) in said channel region is connected to said source region (44a), said first ion-implanted region being of said first conductivity type and forming an enhancement mode region of a predetermined threshold voltage. … A second ion-implanted region (86) in said channel region is connected to said drain region (46a), said second ion-implanted region being of said second conductivity type and forming a depletion mode drain extension. … The ends of the implanted regions defining the channel length are determined by a lateral etching technique by means of which the implantation mask is generated.

公开(公告)号：DE3071936D1

公开(公告)日：1987-04-30

申请号：DE3071936

申请日：1980-12-16

Applicant: IBM

Inventor： DE LA MONEDA FRANCISCO H ,  WILLIAMS THOMAS A

IPC: G11C17/00 ,  G11C11/41 ,  G11C17/08 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8246 ,  H01L23/52 ,  H01L23/528 ,  H01L27/112 ,  H01L27/118 ,  H01L29/78

公开(公告)号：DE3067978D1

公开(公告)日：1984-06-28

申请号：DE3067978

申请日：1980-12-16

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  DE LA MONEDA FRANCISCO H ,  SODERMAN DONALD A

IPC: H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension LD to the drain. However, the introduction of the depletion extension LD introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length LD+L, and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its LD relatively shorter, the companion device will also have its LD correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the LD for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective LD for the right-hand channel is somewhat longer but the effective LD for the left-hand channel is correspondingly shorter, so that the net parallel transconductance for the two devices remains the same as the transconductance for a perfectly symmetric ion-implanted region.

公开(公告)号：DE2739586A1

公开(公告)日：1978-03-23

申请号：DE2739586

申请日：1977-09-02

Applicant: IBM

Inventor： DE LA MONEDA FRANCISCO H ,  KOTECHA HARISH N

IPC: H01L21/822 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/08 ,  H03K17/04 ,  H01L27/08

Abstract: An insulated Gate Field Effect Transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter. Alternate embodiments are disclosed directed to an all N-channel inverter, an all P-channel inverter, and a complementary inverter consisting of a P-channel load device and an N-channel active device.