1.
    发明专利
    未知

    公开(公告)号:DE68919211D1

    公开(公告)日:1994-12-08

    申请号:DE68919211

    申请日:1989-03-29

    Applicant: IBM

    Abstract: An asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronised with the incoming data. Furthermore the serial data receiver is able to share the sampling of the data bit stream between a plurality of shift registers (54) none of which need be clock more than once per data bit period.

    2.
    发明专利
    未知

    公开(公告)号:DE69030953D1

    公开(公告)日:1997-07-24

    申请号:DE69030953

    申请日:1990-03-08

    Applicant: IBM

    Inventor: WINLOW THOMAS

    Abstract: The hardware simulator comprises a plurality of interconnected programmable logic devices (20). The devices are connected via a data bus (22) and a control bus (24). Address signals on the control bus are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the device to the data bus. Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices that are required.

    3.
    发明专利
    未知

    公开(公告)号:DE68919211T2

    公开(公告)日:1995-05-11

    申请号:DE68919211

    申请日:1989-03-29

    Applicant: IBM

    Abstract: An asynchronous serial data receiver for receiving a stream of data bits, characterised by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognising points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronised with the incoming data. Furthermore the serial data receiver is able to share the sampling of the data bit stream between a plurality of shift registers (54) none of which need be clock more than once per data bit period.

Patent Agency Ranking