公开(公告)号：CA1318037C

公开(公告)日：1993-05-18

申请号：CA598607

申请日：1989-05-03

Applicant: IBM

Inventor： PECHANEK GERALD G ,  SHIPPY DAVID J ,  SNEDAKER MARK C ,  WOODWARD SANDRA S

IPC: G06F13/20 ,  G06F13/36 ,  G06F13/40

Abstract: An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.