公开(公告)号：US3387283A

公开(公告)日：1968-06-04

申请号：US52546466

申请日：1966-02-07

Applicant: IBM

Inventor： SNEDAKER MARK C

IPC: G06F9/355 ,  G06F12/06

CPC classification number: G06F9/342 ,  G06F12/0623

公开(公告)号：CA1315890C

公开(公告)日：1993-04-06

申请号：CA598603

申请日：1989-05-03

Applicant: IBM

Inventor： CHISHOLM DOUGLAS R ,  ISEMINGER ROBERT G ,  KELLEY RICHARD A ,  LEUNG WAN L ,  MOYER JAMES T ,  SNEDAKER MARK C

IPC: G06F13/36 ,  G06F13/28

Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The SPD bus, which comprises three sub-buses and a control bus, conducts signals between each IOP and the IOIC in an asynchronous "handshaking" manner. The adapter bus, which comprises two sub-buses and a control bus, conducts signals between the IOIC and the SC in a synchronous manner. The IOIC, interconnected between the SPD bus and adapter bus, functions as a buffer between the faster synchronous bus and the slower asychronous bus. The IOIC also comprises at least one shared DMA facility for executing DMA storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for control information and data to be transmitted between the SC and one of the IOP's and a bus interface coupled to the buffer, to the adapter bus and to the SPD bus for independently transferring the control information and data between the buffer and the SC, on one hand, via the adapter bus, and between the buffer and the one IOP, on the other hand, via the SPD bus. In this manner, the SPD bus can be released for utilization by other IOP's connected thereto during a period of "storage latency" after a DMA storage operation has been initiated by one IOP.

公开(公告)号：CA1318037C

公开(公告)日：1993-05-18

申请号：CA598607

申请日：1989-05-03

Applicant: IBM

Inventor： PECHANEK GERALD G ,  SHIPPY DAVID J ,  SNEDAKER MARK C ,  WOODWARD SANDRA S

IPC: G06F13/20 ,  G06F13/36 ,  G06F13/40

Abstract: An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.

公开(公告)号：CA802460A

公开(公告)日：1968-12-24

申请号：CA802460D

Applicant: IBM

Inventor： SNEDAKER MARK C