公开(公告)号：DE69609430D1

公开(公告)日：2000-08-31

申请号：DE69609430

申请日：1996-02-06

Applicant: IBM

Inventor： PECHANEK GERALD G ,  VASSILIADIS STAMATIS ,  GLOSSNER CLAIR J ,  LARSEN LARRY D

IPC: G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80

Abstract: A plurality of processor elements (PEs) are connected in a cluster by a common instruction bus to an instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is broadcast from the instruction memory over the instruction bus to each PE in the cluster. The instruction includes an opcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on an operand from one of the operand registers in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent. The broadcast instruction includes a destination field that controls the switch in the PE, to dynamically select the destination neighbor PE to which the result is sent. Further, the broadcast instruction includes a target field that controls the switch in the PE, to dynamically select the operand register in the register file of the PE, to which another result received from another neighbor PE in the cluster is stored. In this manner, the instruction broadcast to all the PEs in the cluster, dynamically controls the communication of operands and results between the PEs in the cluster, in a single instruction, multiple data processor array.

公开(公告)号：CA1318037C

公开(公告)日：1993-05-18

申请号：CA598607

申请日：1989-05-03

Applicant: IBM

Inventor： PECHANEK GERALD G ,  SHIPPY DAVID J ,  SNEDAKER MARK C ,  WOODWARD SANDRA S

IPC: G06F13/20 ,  G06F13/36 ,  G06F13/40

Abstract: An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.

公开(公告)号：CA1157567A

公开(公告)日：1983-11-22

申请号：CA373288

申请日：1981-03-18

Applicant: IBM

Inventor： HANFT ROY F ,  PECHANEK GERALD G

IPC: B41J5/30 ,  B41J5/46 ,  G06F3/02 ,  G06F3/023 ,  G06F3/12 ,  G06F17/21 ,  G06K15/08 ,  H03M11/04

Abstract: A text recorder includes a text display device to record text in intelligible form on a typewritten page or line or page-like display in response to character and function identifying signals. A keyboard is included having a plurality of alphabetic, numeric, symbol and function keys for actuation by an operator to produce a keyboard signal unique to the actuated key. A decoder is responsive to keyboard signals from the keyboard to produce character and function identifying signals, such decoder including a word completion facility for producing one of at least two groups of one or more character identifying signals in response to actuation of a selected key on the keyboard, each group of character identifying signals representing a different word ending. The word completion facility includes a selection feature for selecting among the group dependent upon the identity of one or more keys actuated prior to actuation of the selected key. LE9-78-037