公开(公告)号：JPH09213075A

公开(公告)日：1997-08-15

申请号：JP1893096

申请日：1996-02-05

Applicant: IBM

Inventor： YAMAZAKI NORITOSHI ,  MIYATAKE HISATADA

IPC: G11C11/413 ,  G11C7/10 ,  G11C8/04 ,  G11C11/408

Abstract: PROBLEM TO BE SOLVED: To enhance the data transfer rate by adding output signals indicating a carry and a borrow to a pre-decorder and supplying, these signals to a decoder to fetch two data stored in consecutive addresses in one cycle. SOLUTION: When a line 21 is selected by a pre-decoder device 13, lines 25-28 connected to junction points 101, 102 are brought into conduction by the selection of the line 21. Lines 25, 28 among these lines are connect to an INCN, however, since the INCN is a low order when an INC is a high order, they are interrupted at junction points 111, 119. Besides, the line 26 is connected to a BY0 via a junction point 120. Consequently, a first output becomes the BY0 according to an input address. As to the line 27, the junction point 114 with the INC is in a conductive state because the INC is of the high order. Consequently, the line 27 is connected to a BY1 (input address +1) via junction points 114, 121. Thus, the pre-decoder 13 outputs the address in accordance with the input address and addresses of the input address + one address simultaneously by one input address.

公开(公告)号：JPH1166839A

公开(公告)日：1999-03-09

申请号：JP21275897

申请日：1997-08-07

Applicant: IBM

Inventor： TANAKA MASAHIRO ,  MIYATAKE HISATADA ,  MORI YOTARO ,  YAMAZAKI NORITOSHI

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41

Abstract: PROBLEM TO BE SOLVED: To improve a data transfer rate by transferring data plural times in one memory cycle. SOLUTION: A bit line of a memory array l is grouped based on a remainder when the row addresses are divided by the number of groups, and a row address decoding part 4 composing a bit line selection means 3 generates row addresses of the number corresponding to the number of groups according to the row address signal and an access order signal showing the order of the access to the group, and those bit lines are selected by a bit switch 5. Plural latch parts 6a, 6b, 6c each is provided for each group, and the bit line selection means 3 generates plural row addresses consecutive in the same direction referring to the row address signal corresponding to the access order signal.