公开(公告)号：JP2000090439A

公开(公告)日：2000-03-31

申请号：JP25393698

申请日：1998-09-08

Applicant: IBM

Inventor： KANAI TOSHIO ,  USHIO TERUHIKO

IPC: G11B20/10 ,  G11B7/00 ,  G11B7/005 ,  G11B19/28 ,  G11B20/14 ,  G11B27/30 ,  G11B27/34 ,  G11B27/36 ,  G11B19/06

Abstract: PROBLEM TO BE SOLVED: To obtain an exact frequency by saving a measured mark length, measuring the mark continuous with this mark, determining the sum of the saved mark length and the freshly measured mark length and detecting the sum of he lengths of the longest mark and the mark continuous with this mark as the max. mark length. SOLUTION: The total value of the mark lengths is saved from the point of the time the max. value of the sum of the lengths of the continuous marks is measured by a total register 12 for which an arbitrary memory element capable of reading-out and writing is used. A measured value register 14 is capable of using the arbitrary memory element capable of saving at least the previously measured mark lengths and reading out and writing these mark lengths. An arithmetic and logic unit 22 determines the sum of the previously measured mark length and the mark length measured this time, adds the measured value of this time to the tote value and subtracts the max. value from the total value, for which an arbitrary arithmetic circuit capable of making at least addition, subtraction and division is used.

公开(公告)号：JPH08185271A

公开(公告)日：1996-07-16

申请号：JP32471594

申请日：1994-12-27

Applicant: IBM

Inventor： KIGAMI YUJI ,  YAMADA MITSUHARU ,  KANAI TOSHIO ,  ISHIBASHI KAZUYUKI

IPC: G06F3/06 ,  G06F12/08 ,  G11B20/10

Abstract: PURPOSE: To efficiently and simply process the input/output of data at a high speed. CONSTITUTION: Request signals from a host computer 32 are inputted through the I/O 42 of an HDC 30 to a segment handier 36. The segment handier 36 refers to a segment table stored in a table memory 44, selects a segment, sets a segment memory 46 divided into the plural segments through a memory manager 38 and transfers the data to a disk part 11. In the segment handier 36, rules based on the principle of mutual exclusion are stored and determined beforehand and the data are held so as not to overlap the data of the same sector inside the segment memory 46 for the respective segments.

公开(公告)号：MY122099A

公开(公告)日：2006-03-31

申请号：MYPI9804488

申请日：1998-09-30

Applicant: IBM

Inventor： KANAI TOSHIO ,  YASUDA TAKEO ,  TSURUTA KAZUHIRO ,  ICHIHARA WATARU

IPC: G11B7/005 ,  G11B7/00 ,  G11B20/10

Abstract: A METHOD AND APPARATUS FOR REDUCING THE EFFECT OF INTER-WAVE INTERFERENCE ON SIGNALS READ FROM A STORAGE MEDIUM AND TO PRECISELY DIGITIZE THE READ SIGNALS ARE DESCRIBED.AN APPARATUS FOR DIGITIZING A SIGNAL READ FROM A STORAGE MEDIUM ACCORDING TO AN EMBODIMENT OF THE INVENTION,COMPRISES:A PEAK DETECTOR (26),FOR DETECTING A PEAK VALUE FOR AN AMPLITUDE OF A SIGNAL READ FROM THE STORAGE MEDIUM;A THRESHOLD VALUE DETERMINER (28),FOR EMPLOYING THE PEAK VALUE OBTAINED BY THE PEAK DETECTOR TO DETERMINE A DETERMINE A COMPENSATION VALUE THAT IS USED FOR COMPENSATING FOR THE EFFECT OF INTER-WAVE INTERFERENCE ON THE SIGNAL,AND FOR EMPLOYING THE THRESHOLD VALUE CALCULATED BY THE CONVENTIONAL METHOD AND THE COMPENSATION VALUE TO DETERMINE A COMPENSATED THRESHOLD VALUE:AND A DIGITIZATION CIRCUIT (32),FOR DIGITIZATION THE SIGNAL BY USING THE THRESHOLD VALUE DETERMINED BY THE THRESHOLD VALUE DETERMINER.OPTIONALLY AN INTERPOLATOR (24) MAY BE USED TO OBTAIN MORE ACCURATE PEAK VALUE WITH OCCUR BETWEEN SAMPLE POINT. (FIG.2)

公开(公告)号：JP2001101764A

公开(公告)日：2001-04-13

申请号：JP27412999

申请日：1999-09-28

Applicant: IBM

Inventor： TAKASE YASUHIRO ,  MURAKAMI MASAYUKI ,  KANAI TOSHIO

IPC: G06F1/32 ,  G06F1/04 ,  G11B19/00 ,  H03K17/22 ,  H03K19/003

Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of an electronic circuit to operate based on a clock signal when the power is applied. SOLUTION: The power consumption reduction circuit 40 is provided with a clock frequency reduction circuit 41. When a received POR signal is asserted, the clock frequency reduction circuit 41 decreases the frequency of a received CK signal and outputs the CK signal to an IC selection circuit 42. When the received POR is negated, the clock frequency reduction circuit 41 outputs the received CK signal to the IC selection circuit 42 as it is. The signal outputted from the clock frequency reduction circuit 41 is fed to a plurality of ICs 51, 52,..., IC 53 via the IC selection circuit 42.

公开(公告)号：JP2000113606A

公开(公告)日：2000-04-21

申请号：JP28223398

申请日：1998-10-05

Applicant: IBM

Inventor： USHIO TERUHIKO ,  KANAI TOSHIO

IPC: G11B20/18

Abstract: PROBLEM TO BE SOLVED: To revise a bit shift error irrespective of ECC by a method wherein a read signal from a medium is converted into a bit string, and a gray bit having possibilities in an error in the bit string to generate gray bit information, and an error bit is corrected from the information, and the corrected bit string is decoded. SOLUTION: A read channel 11 converts a read signal from a medium 10 into a read data 13 comprising a bit string, and a gray bit 14 having possibilities in an error in a bit string is detected by a gray bit detection circuit 12, and is fed to a decoder 16 via a mark detector 15. The decoder 16 inspects data from the gray bit 14 in a RLL(run length limited) error correction circuit 17, and corrects a discovered data error during transfer to a conversion table 18, and the corrected data are decoded by the conversion table 18. At this time, an error correction is made by an error correction circuit 19 using a conversion table.

公开(公告)号：JP2002358724A

公开(公告)日：2002-12-13

申请号：JP2001363571

申请日：2001-11-29

Applicant: IBM

Inventor： KANAI TOSHIO

IPC: G11B20/10 ,  G11B7/004 ,  G11B7/005

Abstract: PROBLEM TO BE SOLVED: To reduce data read errors due to the offset of read signals. SOLUTION: A data reproducing device uses a level determining unit 10 provided with: a differentiation circuit 12 for obtaining a second order differential V(t) of an output signal V(t) outputted from an AGC 82; an arithmetic circuit (14) for obtaining a time difference between the first intersection Pz0 (time Tz0) of the output signal V(t) and a slice level Vr, and the second intersection Pz2 (time Tz2) of the second order differential V"(t) and a zero level detected in a zero cross detection circuit 84; a comparator circuit (14) for comparing the length of the obtained time difference and prescribed time; and a control means (14) for changing the convergence speed of the error of the amplitude of the output signal V(t) of the AGC(automatic gain control) 82 and a prescribed amplitude value, and the convergence speed of the error of a frequency obtained by the cycle of a time cell set by a PLL 88 and the frequency of the output signal V(t) corresponding to the comparison result of the comparator circuit (14).

公开(公告)号：JP2002057584A

公开(公告)日：2002-02-22

申请号：JP2000236599

申请日：2000-08-04

Applicant: IBM

Inventor： KANAI TOSHIO ,  ROJI MIKIKO

IPC: G11B7/005 ,  G11B20/10 ,  G11B20/18 ,  H03M7/14

Abstract: PROBLEM TO BE SOLVED: To correct the wrong correction by correcting the bit shift of binary data which are read out of media and also generating the information on an uncorrected bit and its correcting direction. SOLUTION: A data reproducer is provided with circuits 24, 26 and 28 which correct the times of cross points between the read and slice signals and a circuit 20 which produces a gray bit that shows a time cell including an uncorrected cross point and another time cell adjacent to the correcting direction of the uncorrected cross point.

公开(公告)号：JP2000112776A

公开(公告)日：2000-04-21

申请号：JP27191298

申请日：1998-09-25

Applicant: IBM

Inventor： USHIO TERUHIKO ,  YAMADA MITSUHARU ,  KANAI TOSHIO ,  KUNIEDA EIJI

IPC: G06F11/10 ,  G06F11/08 ,  G11B20/18 ,  H03M13/00 ,  H03M13/05 ,  H03M13/15 ,  H03M13/27

Abstract: PROBLEM TO BE SOLVED: To provide an error correction system which reduces a time needed for error correction processing in a form of product code and can improve use efficiency of a buffer storage device by efficiently performing data transfer. SOLUTION: This error correction system includes a formatter 20 for generating an ECC block which includes data arrayed in a matrix and at least a line error correction code for each line. A syndrome generator 38 is included between the formatter 20 and a first buffer storage device 22. The syndrome generator 38 generates a syndrome on the basis of each ECC block line from the formatter 20. An ECC block line and a related syndrome are stored in the first buffer storage device 22. Only the syndrome in the first buffer storage device 22 is transferred to a second buffer storage device 24 and an error correction code decoder 26. The first buffer storage device 22 stores data by a bank interleave system and the syndrome is stored at an empty position of the first buffer storage device 22.

公开(公告)号：JPH11328866A

公开(公告)日：1999-11-30

申请号：JP13839098

申请日：1998-05-20

Applicant: IBM

Inventor： KANAI TOSHIO

IPC: G11B20/10 ,  G11B20/14

Abstract: PROBLEM TO BE SOLVED: To exactly binarize a read signal by reproduction of a correct bit string and to reduce a bit error rate at the time of reproduction by evaluating phase error at the intersection point of the read signal from a data memory medium and a slice signal. SOLUTION: A DVS arithmetic circuit 32 generates the slice signal. A level comparator 33 receives the read signal 31 from the data medium and the slice signal from the DVS arithmetic circuit 32 and detects the intersection point of the read signal and the slice signal. A phase comparator 34 selects a time cell in which the detected intersection point is included. The comparator detects the phase difference between the center of this time cell and the intersection point. The time cell is subjected to feedback control by a digital PLL 35. An arithmetic processing circuit 36 evaluates the likelihood from the time cell in which the intersection point is included by using a binarization method using the method of least squares, etc., and using the detected phase difference. The circuit selects the time cell into which the intersection point is required to be included. As a result, the reproduction of the correct bit string information is made possible.

公开(公告)号：JPH11185385A

公开(公告)日：1999-07-09

申请号：JP34236397

申请日：1997-12-12

Applicant: IBM

Inventor： KANAI TOSHIO ,  YASUDA TAKAO ,  TSURUTA KAZUHIRO ,  ICHIHARA WATARU

IPC: G11B7/005 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To reduce the influence of the interference between waveforms of a reproducing signal from a storage medium and to accurately binarize the reproducing signal. SOLUTION: This data slicing circuit 100, for binarizing a reproducing signal from a medium in which data are stored, including a peak detecting circuit 28 for detecting the peak value of the amplitude of reproducing signal from the medium, a threshold deciding circuit 28, for determining a compensating value for compensating the influence of the interference between waveforms of the reproducing signal based on the peak value detected by the peak detecting circuit and determining a threshold value for binarizing the reproducing signal based on the peak value and the compensating value, and a circuit 32 for binarizing the reproducing signal based on the threshold value decided by the threshold deciding circuit, is provided.