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    TWO-STAGE WEIGHTED CAPACITOR CIRCUIT FOR ANALOG-TO- DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS
    1.
    发明专利
    TWO-STAGE WEIGHTED CAPACITOR CIRCUIT FOR ANALOG-TO- DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS 未知

    公开(公告)号：CA1091352A

    公开(公告)日：1980-12-09

    申请号：CA277420

    申请日：1977-04-29

    Applicant: IBM

    Inventor： YEE YEN S

    IPC: H03M1/74 ,  H03M1/00 ,  H03K13/02

    Abstract: TWO-STAGE WEIGHTED CAPACITOR CIRCUIT FOR ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS A two-stage weighted capacitor network for use as an analog-to-digital or digital-to-analog converter is described. A capacitor ladder is included having two similar groups of capacitors connected in parallel. In each group the parallel capacitors have values starting with value C and decreasing in binary fractional amounts C/21, C/22, C/23, C/24 etc. to C/2n-1. The two groups are interconnected through a coupling capacitor of value C/2n-1 and each of the capacitors in the two groups are selectively connected through switches to either a reference voltage or ground potential. A high gain amplifier connected as an inverting amplifier with a 2C capacitor feedback path is connected to the capacitor ladder. When the circuit is used in a digital-to-analog converter, the 2C capacitor is reset and then the digital input pattern, consisting of 2n bits, is manifested by connecting the capacitor ladder switches to the ground potential for "1" bits and leaving the other swithces connected to the reference potential for "0" bits. When the circuit is used in an analog-to-digital converter the output of the amplifier is connected to a comparator which serves as a polarity detector and which feeds a set of control logic. The control logic then sets the switches, which were originally all connected to the analog voltage, in a binary search mode.

    HIGH ACCURACY MOS COMPARATOR
    2.
    发明专利
    HIGH ACCURACY MOS COMPARATOR 未知

    公开(公告)号：CA1072644A

    公开(公告)日：1980-02-26

    申请号：CA278859

    申请日：1977-05-20

    Applicant: IBM

    Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M ,  YEE YEN S

    IPC: G01R19/165 ,  H03K3/353 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03K5/20

    Abstract: HIGH ACCURACY MOS COMPARATOR The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to an FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.

    CHARGE TRANSFER DEVICE DIFFERENCING CIRCUIT
    5.
    发明专利
    CHARGE TRANSFER DEVICE DIFFERENCING CIRCUIT 未知

    公开(公告)号：CA1099409A

    公开(公告)日：1981-04-14

    申请号：CA293097

    申请日：1977-12-14

    Applicant: IBM

    Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M ,  YEE YEN S

    IPC: G01R19/10 ,  G01R29/24 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  H03M1/00 ,  G11C11/08

    Abstract: CHARGE TRANSFER DEVICE DIFFERENCING CIRCUIT A circuit is disclosed for obtaining an output signal proportional to the difference between two charge packet quantities nondestructively. The preferred embodiment includes a substrate with a potential well disposed under a floating gate electrode having charge transfer means for entering and removing charge from the potential well. A first quantity of charge Qa which is stored in the potential well is transferred out of the well at time t1 with a resulting proportional increase in the floating gate voltage which results from capacitor coupling from the charge to the floating gate. At a subsequent time t2 a second charge quantity Qb is transferred into the potential well and causes a proportional decrease in the floating gate voltage. The net change .DELTA.V in the floating gate voltage that results is proportional to the difference between the two charge quantities Q ant Qb.

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