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    1.
    发明专利
    未知

    公开(公告)号：DD152875A5

    公开(公告)日：1981-12-09

    申请号：DD22339380

    申请日：1980-08-19

    Applicant: IBM

    Inventor： FORTINO ANDRES G ,  GEIPEL HENRY J ,  HELLER LAWRENCE G ,  SILVERMANN RONALD

    IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78 ,  G11C11/40

    Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.

    RANDOM LOGIC ERROR DETECTING SYSTEM FOR DIFFERENTIAL LOGIC NETWORKS
    5.
    发明专利
    RANDOM LOGIC ERROR DETECTING SYSTEM FOR DIFFERENTIAL LOGIC NETWORKS 未知

    公开(公告)号：CA1231758A

    公开(公告)日：1988-01-19

    申请号：CA485182

    申请日：1985-06-25

    Applicant: IBM

    Inventor： GRIFFIN WILLIAM R ,  HELLER LAWRENCE G ,  HOROWITZ PETER N

    IPC: G01R31/28 ,  G06F11/00

    Abstract: Random Logic Error Detecting System For Differential Logic Networks A system for testing a differential logic network is provided which includes a differential exclusive OR circuit having a plurality of inputs for receiving complementary signals from the differential logic network and first and second output terminals and means, e.g., a conventional exclusive OR circuit, for determining the voltage difference between the first and second output terminals to indicate the presence or absence of a fault or error in the differential logic network under test.

    CHARGE TRANSFER STORAGE SYSTEMS
    6.
    发明专利
    CHARGE TRANSFER STORAGE SYSTEMS 未知

    公开(公告)号：CA1130002A

    公开(公告)日：1982-08-17

    申请号：CA337647

    申请日：1979-10-15

    Applicant: IBM

    Inventor： HELLER LAWRENCE G

    IPC: G11C17/00 ,  G11C11/35 ,  G11C14/00 ,  G11C16/04 ,  G11C19/28 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/112 ,  G11C11/40 ,  H01L27/04

    Abstract: CHARGE TRANSFER STORAGE SYSTEMS Storage systems are provided with memory cells made of devices having different voltage thresholds for storing information permanently or semipermanently. The devices are arranged adjacent to each other and communicating with a different region in a semiconductor substrate. Information is sensed by detecting the charge transferred from a selected cell to the diffusion region. In an embodiment of the invention, a P-type substrate has an N+ diffusion region formed therein with a plurality of adjacent and parallelly arranged word lines insulated from the substrate and disposed adjacent to the N+ diffusion region. A P+ region, preferably implanted into the substrate, is disposed under selected segments of the word lines to provide devices having a first or high threshold voltage magnitude. The remaining devices which are not associated with a P+ region have a second or low threshold voltage magnitude. By applying a voltage of the same magnitude to each of the word lines, potential wells are formed which are filled by charge or carriers from the diffusion region. Since the potential wells associated with the high threshold devices hold less charge than do BU-9-78-009 the low threshold devices, a charge or voltage sensing circuit connected to the N+ diffusion region is used to detect the amount of charge flowing between the wells and the diffusion region to thus identify the high and low threshold devices when the voltage on the selected word line is decreased. By eliminating the P+ regions and storing charge, e. g., electrons, at selected locations under the word lines in dual insulating layers, the cells may BU be electrically programmable. BU-9-78-009

    8.
    发明专利
    未知

    公开(公告)号：DE3576052D1

    公开(公告)日：1990-03-22

    申请号：DE3576052

    申请日：1985-12-03

    Applicant: IBM

    Inventor： GRIFFIN WILLIAM R ,  HELLER LAWRENCE G ,  HOROWITZ PETER N

    IPC: G01R31/28 ,  G06F11/00

    Abstract: A system for testing a differential logic network (10) is provided which includes a differential exclusive OR circuit (12) having a plurality of inputs for receiving complementary' signals A,A;B,) from the differential logic network and first and second output terminals (Q,Q) and means, including a conventional exclusive OR circuit (26), for determining the voltage difference between the first and second output terminals (Q,Q) to indicate the presence or absence of a fault or error in the differential logic network (10) under test.

    LOGIC CONTROLLED CHARGE TRANSFER DEVICE TRANSVERSAL FILTER EMPLOYING SIMPLE WEIGHTING
    10.
    发明专利
    LOGIC CONTROLLED CHARGE TRANSFER DEVICE TRANSVERSAL FILTER EMPLOYING SIMPLE WEIGHTING 未知

    公开(公告)号：CA1097811A

    公开(公告)日：1981-03-17

    申请号：CA275386

    申请日：1977-03-30

    Applicant: IBM

    Inventor： HELLER LAWRENCE G

    IPC: H03H15/02 ,  G11C11/40

    Abstract: A LOGIC CONTROLLED CHARGE TRANSFER DEVICE TRANSVERSAL FILTER EMPLOYING SIMPLE WEIGHTING A transversal filter structure employing charge transfer techniques which are embodied in charge-coupled-devices although bucket brigade devices may also be used. In the structure an input analog signal is time sampled and for each sample a sequence of charge packets Q/2, Q/4, Q/8...Q/2n is generated. Each sequence of charge packets is entered into a serial chargecoupled-device register and each separate charge packet is then entered into a plurality of n parallel charge-coupled-device registers according to the fractional distribution, i.e. Q1/2, Q2/2, Q3/2...Qk/2 in one register, Q1/4, Q2/4, Q3/4...Qk/4 in another register, up to Q1/2n, Q2/2n, Q3/2n...Qk/2n in a last register. The charge packets in the parallel registers represent the time sampled analog input signal divided by 1, 2, 4, 8,...2n respectively, and tap weights of +1, -1 and 0 are applied by means of logic control and FET switches. The tap weights are bussed together, summed and differenced and the difference signal is the filter output signal.

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