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    2.
    发明专利
    未知

    公开(公告)号：DE2359184A1

    公开(公告)日：1974-06-06

    申请号：DE2359184

    申请日：1973-11-28

    Applicant: IBM

    Inventor： YUN BOB HONG

    IPC: G01R29/24 ,  G01R19/155 ,  G01R31/00 ,  G01R31/26 ,  G01R31/28 ,  G01R29/00

    Abstract: 1400960 Locating centroid of charge distribution INTERNATIONAL BUSINESS MACHINES CORP 13 Nov 1973 [4 Dec 1972] 52613/73 Heading G1U By applying a pulse of A.C. (of the order of 100 kc/s) superimposed upon a D.C. bias across a dielectric, charge is injected into the dielectric, and the centroid of the distribution of charge that remains trapped in the dielectric at the end of the pulse is determined by measuring the amount of charge injected and the resulting change in potential across the dielectric. According to classical electrostatic theory the potential across a capacitor varies linearly with charge (V=q/c) and all the charge is thought of as lying on the surface of the dielectric. With modern semi-conductor dielectrics, this theory is too simplistic, since it is found that a current (holes or electrons) actually flows through the dielectric upon the application of a suitable potential across it, and moreover, that when the potential is removed some of the charge constituting the current remains trapped, even after the potential across the dielectric is restored to zero. The presence of this trapped charge, and its distribution, affect the capacitive properties of the dielectric.

    METHOD FOR MAKING FINE DEEP DIELECTRIC ISOLATION
    3.
    发明专利
    METHOD FOR MAKING FINE DEEP DIELECTRIC ISOLATION 未知

    公开(公告)号：DE3177048D1

    公开(公告)日：1989-06-08

    申请号：DE3177048

    申请日：1981-02-25

    Applicant: IBM

    Inventor： VENKATARAMAN KRISHNAMUR ,  YUN BOB HONG

    IPC: H01L21/76 ,  H01L21/033 ,  H01L21/308 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73 ,  H01L21/00

    Abstract: The invention relates to a method for making fine, deep dielectric isolation. The method involves forming a first layer (16) of material on the silicon body (10, 12, 14) over a first set of alternately designated device regions. A conformal coating (18) is deposited over the first layer (16) and on the silicon body (10, 12, 14) included in a second set of alternately designated device regions and the designated isolation regions. The thickness of conformal coating (18) is chosen to be substantially the width of the planned isolation between device regions. A second layer (20) is then deposited over conformal coating (18). First layer (16) and conformal coating (18) are composed of different materials. The topmost surface comprising of second layer (20) and conformal coating (18) is planarized by removing partially second layer (20) and conformal coating (18) from first layer (16) wherein the second set of alternately designated device regions in silicon body (10, 12, 14) are covered by conformal coating (18) and second layer (20) with portions of the conformal coating separating the covers for the first and second set of device regions. The portions of conformal coating (18) separating the covers are removed down to the silicon body (14) over the designated isolation regions. A groove (22) is then etched in the silicon body (10, 12, 14) using the covers as the etch mask. The groove (22) is etched to the desired depth of the dielectric isolation in the designated isolation regions and then is filled typically by thermal oxidation.

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