公开(公告)号：WO2009117255A3

公开(公告)日：2009-12-30

申请号：PCT/US2009036091

申请日：2009-03-05

Applicant: IBM ,  CHAPPLE-SOKOL JONATHAN D ,  DELIBAC DANIEL A ,  ZHONG-XIANG HE ,  LEE TOM C ,  MURPHY WILLIAM J ,  SULLIVAN TIMOTHY D ,  THOMAS DAVID C ,  VANSLETTE DANIEL S

Inventor： CHAPPLE-SOKOL JONATHAN D ,  DELIBAC DANIEL A ,  ZHONG-XIANG HE ,  LEE TOM C ,  MURPHY WILLIAM J ,  SULLIVAN TIMOTHY D ,  THOMAS DAVID C ,  VANSLETTE DANIEL S

IPC: H01L21/4763

CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack (360L, Figure 5) comprising, from bottom to top, a low-oxygen-reactivity metal layer (10), a bottom transition metal layer (20), a bottom transition metal nitride layer (30), an aluminum-copper layer (40), an optional top transition metal layer (50), and a top transition metal nitride layer (60). The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen- reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract translation: 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 从底部到顶部包含低氧反应性金属层（10），底部过渡金属层（20），底部过渡金属氮化物层（30），铝合金（30）的金属层堆叠（360L，图5） （40），可选的顶部过渡金属层（50）和顶部过渡金属氮化物层（60）。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和介电材料层之间的化合物的形成，从而提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

公开(公告)号：GB2512783B

公开(公告)日：2016-08-03

申请号：GB201412764

申请日：2013-01-03

Applicant: IBM

Inventor： EDWARD C COONEY ,  JEFFREY P GAMBINO ,  ZHONG-XIANG HE ,  TOM C LEE ,  XIAO HU LIU

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.