公开(公告)号：CA1128364A

公开(公告)日：1982-07-27

申请号：CA353162

申请日：1980-06-02

Applicant: IBM

Inventor： JACKSON TIMOTHY ,  MALKEMES CHARLES D ,  ZIPOY WILLIAM L

IPC: B41J2/51 ,  B41J19/18 ,  G06K15/00 ,  G06K15/08 ,  G06K15/10 ,  B41J3/12

Abstract: There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a signal a determined time after being programmed. The control logic responds to print emitter signals manifesting an incremental movement of the print head by interrupting the microprocessor. The microprocessor then programs the timer to provide signals after a programmed delay time to again interrupt the microprocessor. The microprocessor then provides signals causing the operation of the print elements on print head. BC9-79-024

公开(公告)号：CA1148265A

公开(公告)日：1983-06-14

申请号：CA352373

申请日：1980-05-21

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  JACKSON TIMOTHY ,  ZIPOY WILLIAM L

IPC: G06F13/28 ,  G06F3/00 ,  G06F3/06 ,  G06F9/22 ,  G06F9/26 ,  G06F9/46 ,  G06F11/34 ,  G06F13/00

Abstract: HIGH PERFORMANCE I/O CONTROLLER FOR TRANSFERRING DATA BETWEEN A HOST PROCESSOR AND MULTIPLE I/O UNITS An I/O controller for transferring data between a host processor and an I/O unit is disclosed comprising: a random access storage unit located in the I/O controller for storing data; first selectively operable data transfer circuitry for providing a data transfer path between the host processor and the controller storage unit; second selectively operable data transfer circuitry for providing a data transfer path between the controller storage unit and the I/O unit; first storage accessing circuitry for supplying addresses to the controller storage unit and selection signals to the second data transfer circuitry for enabling the transfer of data between the controller storage unit and the I/O unit; second storage accessing circuitry for supplying host processor main storage addresses to the host processor, controller storage addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data between the host processor main storage unit and the controller storage unit in a first data transfer mode; third storage accessing circuitry responsive to addresses received from the host processor for supplying addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data between the host processor and the controller storage unit in a second data transfer mode; and interleaving control circuitry for enabling the second mode data transfers to be interleaved with the first mode data transfers.