公开(公告)号：DE10342028A1

公开(公告)日：2004-03-25

申请号：DE10342028

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEDGE SURYANARAYAN ,  TONTI WILLIAM

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/768

Abstract: An integrated circuit is manufactured by doping portion of semiconductor substrate with nitrogen and a charge carrier dopant source, forming a thin dielectric on the doped portion of the substrate, forming a first separated from the substrate by the thin dielectric, and forming a second conductor coupled to the doped portion of the substrate. The thin dielectric is subjected to breakdown upon application of a breakdown voltage. An Independent claim is also included for an integrated circuit including an anti-fuse.

公开(公告)号：DE10310571A1

公开(公告)日：2003-10-02

申请号：DE10310571

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  MCSTAV KEVIN

IPC: H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/108

Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

公开(公告)号：DE10342028B4

公开(公告)日：2016-04-07

申请号：DE10342028

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEDGE SURYANARAYAN ,  TONTI WILLIAM

IPC: H01L21/82 ,  H01L23/525 ,  H01L21/768 ,  H01L27/10

Abstract: Verfahren zum Ausbilden einer integrierten Schaltung, mit einer Antifuse auf einem Halbleitersubstrat, umfassend: Dotieren einer dotierten Wanne (30) eines Halbleitersubstrats (14) mit Stickstoff und einem Ladungsträger-Dotierstoff vom Ladungsträgertyp der dotierten Wanne, um einen Dotierbereich (28) zu erzeugen, wobei beim Dotieren ein Verhältnis des Ladungsträger-Dotierstoffs zum Stickstoff zwischen ca. 0,5:1 und 1,3:1 verwendet wird; Ausbilden eines dünnen Dielektrikums (16) auf dem Dotierbereich (28) des Halbleitersubstrats; Ausbilden eines durch das dünne Dielektrikum von dem Halbleitersubstrat getrennten ersten Leiters (12); Ausbilden eines leitend an den Dotierbereich (28) des Halbleitersubstrats gekoppelten zweiten Leiters (24), wobei an dem dünnen Dielektrikum (16) bei Anlegen einer Durchbruchsspannung ein Durchbruch auftritt.

公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

公开(公告)号：DE10310569A1

公开(公告)日：2003-10-02

申请号：DE10310569

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  LEE KIL-HO ,  MANDELMAN JACK A ,  MCSTAY KEVIN ,  RENGARAJAN RAJESH

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

Abstract: Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants-an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

公开(公告)号：EP1917682A4

公开(公告)日：2009-09-30

申请号：EP06813862

申请日：2006-08-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

IPC: H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/165

公开(公告)号：EP1676296A4

公开(公告)日：2008-08-20

申请号：EP04795664

申请日：2004-10-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L29/10 ,  H01L20060101 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：EP1927128A4

公开(公告)日：2009-01-28

申请号：EP06804017

申请日：2006-09-22

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

公开(公告)号：EP1805796A4

公开(公告)日：2008-10-01

申请号：EP05800298

申请日：2005-09-29

Applicant: IBM ,  TOSHIBA KK

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  OH SANG-HYUN ,  PANDA SIDDHARTHA ,  RAUSCH WERNER A ,  SATO TSUTOMU ,  UTOMO HENRY K

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A field effect transistor (FET) (10) is provided which includes a gate stack (29), a pair of first spacers (32) disposed over sidewalls of the gate stack (29 and a pair of semiconductor alloy regions (39) disposed on opposite sides of and spaced a first distance from the gate stack (29). Source and drain regions (24) of the FET (10) are at least partly disposed in the semiconductor alloy regions (39; and spaced a second distance from the gate stack (29) by a corresponding spacer of the pair of first spacers (32), which may be different from the first distance. The FET (10) may also include second spacers (34) disposed on the first spacers (32), and silicide regions (40) at least partly overlying the semiconductor alloy regions (39), wherein the silicide regions (40) are spacec from the gate stack (29) by the first and second spacers (32, 34).