公开(公告)号：DE102007007132A1

公开(公告)日：2007-09-13

申请号：DE102007007132

申请日：2007-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： GABOR ALLEN H ,  MANN RANDY W ,  SCHEER STEVEN ,  SCHROEDER UWE PAUL

IPC: H01L27/11 ,  H01L21/28 ,  H01L21/8244 ,  H01L27/112

Abstract: The arrangement has a line (126) with a rectangular tip (128) that is provided opposite to another rectangular tip (124) of another line (122) for forming a tip-to-tip characteristic (120), where the two lines are formed as an individual continuous line in a lithographic step. A contact-like characteristic is formed on the individual continuous line for separation of the individual continuous line. The two rectangular tips of the two lines are provided in another lithographic step. The two lines include polysilicon conductor, where the two lines overlap a diffusion region, respectively. An independent claim is also included for the production of a semiconductor arrangement.

公开(公告)号：JP2004266269A

公开(公告)日：2004-09-24

申请号：JP2004020551

申请日：2004-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LAAS W LIEBMANN ,  GABOR ALLEN H ,  GORDON RONALD L ,  FONSECA CARLOS ,  BURKHARDT MARTIN

IPC: G03F1/00 ,  G06F17/50 ,  H01L21/027 ,  G03F1/08

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/70125 ,  G06F17/5068 ,  G06F2217/12

Abstract: PROBLEM TO BE SOLVED: To provide a method to design a mask for integrated circuit (IC) design layout drawing in order to efficiently configure sub-resolution assist features (SRAFs) corresponding to an optimally structured annular illumination light source of a lithography projection system. SOLUTION: A critical pitch relative to an IC design is specified, and the optimal inner radial coordinate σ inner and the optimal outer radial coordinate σ outer of an annular illumination light source are determined so that an image projected through a mask is optimized throughout the pitch range in a design layout. A relation is given to determine the optimal inner radius and the optimal outer radius for the annular illumination light source. The number and positions of sub-resolution assist features (SRAFs) is added to the mask design so that the obtained pitch range almost corresponds to the critical pitch. This method to configure SRAFs so that an image has optimal characteristics such as a good contrast and a good focal depth takes a short time. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种设计用于集成电路（IC）设计布局图的掩模的方法，以便有效地配置对应于最佳结构的光刻的环形照明光源的子分辨率辅助特征（SRAF） 投影系统

解决方案：规定了相对于IC设计的临界间距，并且环形照明的最佳内径向坐标σ内和最佳外径向坐标σ外 确定光源，使得通过掩模投射的图像在设计布局中在整个间距范围内被优化。 给出了确定环形照明光源的最佳内半径和最佳外半径的关系。 将子分辨率辅助特征（SRAF）的数量和位置添加到掩模设计中，使得所获得的间距范围几乎对应于临界间距。 这种配置SRAF的方法使得图像具有最佳特征，例如良好的对比度和良好的聚焦深度需要很短的时间。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：DE112012004187T5

公开(公告)日：2014-06-26

申请号：DE112012004187

申请日：2012-05-29

Applicant: IBM

Inventor： RAGHUNATHAN SUDHARSHANAN ,  KANAKASABAPATHY SIVANANDA K ,  JUNG RYAN O ,  GABOR ALLEN H ,  BURNS SEAN D ,  MCLELLAN ERIN CATHERINE

IPC: H01L21/027

Abstract: Eine Ausführungsform der vorliegenden Erfindung stellt ein Verfahren zum Bilden einer Halbleitereinheit mit mehreren kritischen Abmessungen in einem Prozess für einen Transfer von Abbildungen von Seitenwänden bereit. Das Verfahren beinhaltet ein Bilden einer dielektrischen Schicht mit mehreren Niveaus über einer Vielzahl von Mandrells, wobei die dielektrische Schicht mit mehreren Niveaus eine Vielzahl von Bereichen aufweist, welche die Vielzahl von Mandrells bedecken, wobei die Vielzahl von Bereichen der dielektrischen Schicht mit mehreren Niveaus unterschiedliche Dicken aufweist; ein Ätzen der Vielzahl von Bereichen der dielektrischen Schicht mit mehreren Niveaus zu Abstandshaltern, indem ein gerichteter Ätzprozess angewendet wird, wobei die Abstandshalter unmittelbar neben Seitenwänden der Vielzahl von Mandrells gebildet werden und unterschiedliche Breiten aufweisen, die mit den unterschiedlichen Dicken der Vielzahl von Bereichen der dielektrischen Schicht mit mehreren Niveaus korrespondieren; ein Entfernen der Vielzahl von Mandrells zwischen den Abstandshaltern; sowie ein Transferieren von Abbildungen der Unterseiten der Abstandshalter in eine oder mehrere Schichten unterhalb der Abstandshalter.

公开(公告)号：GB2508758B

公开(公告)日：2015-12-09

申请号：GB201404138

申请日：2012-05-29

Applicant: IBM

Inventor： RAGHUNATHAN SUDHARSHANAN ,  KANAKASABAPATHY SIVANANDA ,  JUNG RYAN O ,  GABOR ALLEN H ,  BURNS SEAN D ,  MCLELLAN ERIN CATHERINE

IPC: H01L21/82 ,  H01L21/311

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.

公开(公告)号：GB2508758A

公开(公告)日：2014-06-11

申请号：GB201404138

申请日：2012-05-29

Applicant: IBM

Inventor： RAGHUNATHAN SUDHARSHANAN ,  KANAKASABAPATHY SIVANANDA ,  JUNG RYAN O ,  GABOR ALLEN H ,  BURNS SEAN D ,  MCLELLAN ERIN CATHERINE

IPC: H01L21/033 ,  H01L21/311

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in- between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.