公开(公告)号：DE102005034667A1

公开(公告)日：2006-03-23

申请号：DE102005034667

申请日：2005-07-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HUMMEL JOHN P ,  KASKO IHAR ,  LOW KIA-SENG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/22

Abstract: The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such as TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.

公开(公告)号：DE102004043855A1

公开(公告)日：2005-05-19

申请号：DE102004043855

申请日：2004-09-10

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STOJAKOVIC GEORGE ,  RANADE RAJIV M ,  KASKO IHAR ,  NUETZEL JOACHIM ,  MILKOVE KEITH RAYMOND ,  ALLEN RUSSEL D ,  LEE YOUNG HOON

IPC: G11C11/22 ,  H01L21/00 ,  H01L27/22 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L43/08 ,  H01L43/12

Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

公开(公告)号：DE102006023195A1

公开(公告)日：2006-11-30

申请号：DE102006023195

申请日：2006-05-17

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC

Inventor： KASKO IHAR

IPC: H01L27/22

公开(公告)号：DE102005034386A1

公开(公告)日：2006-03-16

申请号：DE102005034386

申请日：2005-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IHAR ,  SARMA CHANDRASEKHAR

IPC: H01L23/544 ,  G03F7/00 ,  H01L27/22

Abstract: A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may extend into lower layers, including the workpiece, of the semiconductor device. An opaque material layer is deposited, and depressions are formed in the opaque layer over the deep alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

公开(公告)号：DE102004043855B4

公开(公告)日：2011-04-21

申请号：DE102004043855

申请日：2004-09-10

Applicant: IBM ,  QIMONDA AG

Inventor： STOJAKOVIC GEORGE ,  RANADE RAJIV M ,  KASKO IHAR ,  NUETZEL JOACHIM ,  MILKOVE KEITH RAYMOND ,  ALLEN RUSSEL D ,  LEE YOUNG HOON

IPC: H01L43/08 ,  G11C11/22 ,  H01L21/00 ,  H01L27/22 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L43/12