公开(公告)号：DE102004030860A1

公开(公告)日：2005-02-03

申请号：DE102004030860

申请日：2004-06-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

IPC: H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/532 ,  H01L27/22

Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

公开(公告)号：DE102004030860B4

公开(公告)日：2007-05-31

申请号：DE102004030860

申请日：2004-06-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/532 ,  H01L27/22

Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

公开(公告)号：DE102004043855A1

公开(公告)日：2005-05-19

申请号：DE102004043855

申请日：2004-09-10

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STOJAKOVIC GEORGE ,  RANADE RAJIV M ,  KASKO IHAR ,  NUETZEL JOACHIM ,  MILKOVE KEITH RAYMOND ,  ALLEN RUSSEL D ,  LEE YOUNG HOON

IPC: G11C11/22 ,  H01L21/00 ,  H01L27/22 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L43/08 ,  H01L43/12

Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

公开(公告)号：DE102004034822A1

公开(公告)日：2005-03-03

申请号：DE102004034822

申请日：2004-07-19

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NING XIAN JAY ,  NUETZEL JOACHIM ,  WILLE WILLIAM

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L21/768

Abstract: A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.

公开(公告)号：DE102004027663A1

公开(公告)日：2005-03-24

申请号：DE102004027663

申请日：2004-06-07

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ARNDT CHRISTIAN ,  COSTRINI GREG ,  GAIDIS MICHAEL ,  NING XIANG JAY ,  NUETZEL JOACHIM

IPC: H01L21/768 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/12 ,  G11C11/15

Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.

公开(公告)号：WO02095827A3

公开(公告)日：2003-08-21

申请号：PCT/DE0201651

申请日：2002-05-07

Applicant: INFINEON TECHNOLOGIES AG ,  NUETZEL JOACHIM ,  SCHWARZL SIEGFRIED

Inventor： NUETZEL JOACHIM ,  SCHWARZL SIEGFRIED

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/22

CPC classification number: H01L27/222

Abstract: The invention relates to an especially simple method for producing semiconductor storage devices (1). Said method enables diffusion barriers (30f) to be formed between laterally arranged storage elements (20) by depositing a material region for a first passivation region (30) and by subsequently polishing with a barrier layer on an essentially common level (26a) of the storage elements (20).

Abstract translation: 它是呈现的半导体存储器装置的一种特别简单的制造方法（1），其中扩散阻挡层（30F）横向布置的存储元件（20）通过在基本上相同的水平上沉积材料区域用于第一钝化区（30），并通过随后的抛光停止（间 26a）的所述存储器元件被其形成。

公开(公告)号：WO02095794A3

公开(公告)日：2003-10-16

申请号：PCT/DE0201818

申请日：2002-05-21

Applicant: INFINEON TECHNOLOGIES AG ,  NUETZEL JOACHIM ,  SCHLOESSER TILL ,  SCHWARZL SIEGFRIED ,  WURM STEFAN

Inventor： NUETZEL JOACHIM ,  SCHLOESSER TILL ,  SCHWARZL SIEGFRIED ,  WURM STEFAN

IPC: H01L27/10 ,  H01L20060101 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L27/222 ,  B82Y10/00

Abstract: The aim of the invention is to integrate a capacitor device (40) in the area of a semiconductor memory device while using particularly few process steps. To this end, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) to be provided are to be structured directly underneath or directly above the material area (30) that accommodates the memory elements (20). These electrode devices are to be structured so that at least one portion of the material area (30) that accommodates the memory elements (20) functions as a part of the respective dielectric (45) between the electrode devices (43, 44).

Abstract translation: 用于在具有特别少的工艺步骤的半导体存储器件的区域中的积分电容器装置的提出，要被提供的电容器装置的正下方或正上方的下电极装置和的上部电极装置具有材料区auzubilden存储器元件，使得由至少具有存储器元件材料区域的一部分 作用在电极装置之间的各个介质的至少一部分。

公开(公告)号：DE102004041679A1

公开(公告)日：2006-02-23

申请号：DE102004041679

申请日：2004-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NUETZEL JOACHIM ,  MUEMMLER KLAUS ,  THIES ANDREAS ,  KAMM FRANK-MICHAEL

IPC: G03F7/00 ,  G03F7/09 ,  H01L21/308 ,  H01L21/8242

Abstract: A method of lithographic production of structures in a radiation-sensitive layer, especially for semiconductor elements, comprises forming a radiation-absorbing layer (1) on or in the substrate (10) and radiating at an angle to the normal so that at least part of the structure in the sensitive layer (20) is shadowed. An independent claim is also included for a structured semiconductor substrate for the above method.

公开(公告)号：DE102004027691A1

公开(公告)日：2006-01-05

申请号：DE102004027691

申请日：2004-06-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  NUETZEL JOACHIM

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/8242 ,  H01L29/786 ,  H01L31/20

Abstract: Process for producing a web of a semiconductor material The invention relates to a process for producing two webs of a semiconductor material, in which a sacrificial web of a first material is produced on a semiconductor substrate, in which the first material is selected in such a way that the crystal structure of the semiconductor substrate is substantially transferred to the sacrificial web, in which the two webs of a semiconductor material are deposited on two opposite side walls of the sacrificial web, in which the crystal structure of the sacrificial web is substantially transferred to the crystal structure of the webs, and in which the sacrificial webs are then removed.

公开(公告)号：DE10125594A1

公开(公告)日：2002-12-05

申请号：DE10125594

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NUETZEL JOACHIM ,  SCHWARZL SIEGFRIED ,  SCHLOESSER TILL ,  WURM STEFAN

IPC: H01L27/10 ,  H01L20060101 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: The aim of the invention is to integrate a capacitor device (40) in the area of a semiconductor memory device while using particularly few process steps. To this end, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) to be provided are to be structured directly underneath or directly above the material area (30) that accommodates the memory elements (20). These electrode devices are to be structured so that at least one portion of the material area (30) that accommodates the memory elements (20) functions as a part of the respective dielectric (45) between the electrode devices (43, 44).