公开(公告)号：DE69834856D1

公开(公告)日：2006-07-27

申请号：DE69834856

申请日：1998-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： COHEN SUSAN ,  COOPER EMMANUEL I ,  PENNER KLAUS ,  RATH DAVID L ,  SRIVASTAVA KAMALESH K

IPC: H01L21/304 ,  H01L21/306 ,  B08B3/12 ,  H01L21/00

Abstract: An efficient cleaning process of microelectronics devices requires lower levels of megasonic power, lower temperature and much lower concentrations of chemicals. The method controls the effectiveness of megasonics-assisted cleaning of microelectronics devices by securing a gas concentration level in the cleaning solution, such that at the process temperature the solution is partially saturated with the gas. The gas concentration can be controlled either at the plan-wide level or, preferably, at the point of use. In the latter case, two water supply inputs are provided, one of vacuum-degassed water and the other of gas-saturated water. Process water in the desired gas concentration is then obtained by mixing water from the two sources in an appropriate ratio, which resulting mixture is fed to the wafer cleaning vessel.

公开(公告)号：DE69830141T2

公开(公告)日：2006-01-19

申请号：DE69830141

申请日：1998-12-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  TOSHIBA KK

Inventor： ILG MATTHIAS ,  KLEINHENZ RICHARD L ,  NADAHARA SOICHI ,  NUNEZ RONALD W ,  PENNER KLAUS ,  ROITHNER KLAUS ,  SRINIVASAN RADHIKA ,  SUGIMOTO SHIGEKI

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: An improved method for forming semiconductor substrates using BSG avoids the problems associated with conventional TEOS hard mask techniques. The methods comprises providing a semiconductor substrate 1 and applying a conformal layer of borosilicate glass (BSG) 40 on the substrate. A photoresist layer 60 is then formed over the BSG layer and pattern to expose a desired portion of a layer underlying the photoresist layer. Anisotropical etching is then performed through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers 10, 20 are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers 50 may be applied over the BSG layer between the BSG layer and the photoresist layer. The method is especially useful for forming deep trenches in silicon substrates with pad dielectric layers.

公开(公告)号：DE69830141D1

公开(公告)日：2005-06-16

申请号：DE69830141

申请日：1998-12-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  TOSHIBA KK

Inventor： ILG MATTHIAS ,  KLEINHENZ RICHARD L ,  NADAHARA SOICHI ,  NUNEZ RONALD W ,  PENNER KLAUS ,  ROITHNER KLAUS ,  SRINIVASAN RADHIKA ,  SUGIMOTO SHIGEKI

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: An improved method for forming semiconductor substrates using BSG avoids the problems associated with conventional TEOS hard mask techniques. The methods comprises providing a semiconductor substrate 1 and applying a conformal layer of borosilicate glass (BSG) 40 on the substrate. A photoresist layer 60 is then formed over the BSG layer and pattern to expose a desired portion of a layer underlying the photoresist layer. Anisotropical etching is then performed through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers 10, 20 are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers 50 may be applied over the BSG layer between the BSG layer and the photoresist layer. The method is especially useful for forming deep trenches in silicon substrates with pad dielectric layers.

公开(公告)号：DE69834856T2

公开(公告)日：2006-12-14

申请号：DE69834856

申请日：1998-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： COHEN SUSAN ,  COOPER EMMANUEL I ,  PENNER KLAUS ,  RATH DAVID L ,  SRIVASTAVA KAMALESH K

IPC: H01L21/304 ,  H01L21/306 ,  B08B3/12 ,  H01L21/00

Abstract: An efficient cleaning process of microelectronics devices requires lower levels of megasonic power, lower temperature and much lower concentrations of chemicals. The method controls the effectiveness of megasonics-assisted cleaning of microelectronics devices by securing a gas concentration level in the cleaning solution, such that at the process temperature the solution is partially saturated with the gas. The gas concentration can be controlled either at the plan-wide level or, preferably, at the point of use. In the latter case, two water supply inputs are provided, one of vacuum-degassed water and the other of gas-saturated water. Process water in the desired gas concentration is then obtained by mixing water from the two sources in an appropriate ratio, which resulting mixture is fed to the wafer cleaning vessel.

公开(公告)号：DE10063600A1

公开(公告)日：2002-07-04

申请号：DE10063600

申请日：2000-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RAVIKUMAR RAMACHANDRAN ,  KRAUSE HOLGER ,  NICHTERWITZ MARION ,  NITSCHKE CHRISTIANE ,  PENNER KLAUS

IPC: C30B33/10 ,  H01L21/306

Abstract: Process for etching a wafer (8) using an aqueous solution of H2SO4 and H2O2 comprises removing a sample from a wafer processing tank (2) at regular intervals; comparing the concentration of HF in the solution in the sample using a comparing unit (9) with a reference value; and acquiring a concentration signal in a dosing pump (4) for the introduction of HF from an HF supply container (3) into the solution or a signal for exposing the wafer to cleaning. An Independent claim is also included for a device for etching a wafer. Preferred Features: Etching of the wafer is carried out in an immersion bath using an HF concentration of 5-50 ppm. The bath has a temperature of 20-60 deg C.

公开(公告)号：DE10029036C1

公开(公告)日：2001-08-09

申请号：DE10029036

申请日：2000-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MORHARD KLAUS-DIETER ,  SPERL IRENE ,  PENNER KLAUS

IPC: H01L21/8242

公开(公告)号：JPH10242107A

公开(公告)日：1998-09-11

申请号：JP1540698

申请日：1998-01-28

Applicant: IBM ,  SIEMENS AG

Inventor： COHEN SUSAN ,  COOPER EMMANUEL I ,  PENNER KLAUS ,  RATH DAVID L ,  SRIVASTAVA KAMALESH K

IPC: H01L21/304 ,  B08B3/12 ,  H01L21/00

Abstract: PROBLEM TO BE SOLVED: To control the effectiveness of a magnetic aided cleaning for a microelectronics circuit device by establishing the gas concn. level in a cleaning soln. so that the soln. is partly saturated with a gas at a given process temp. SOLUTION: A deionized water source 101 feeds a water to a vacuum degassed unit 102 to remove a gas dissolved in the fed water. The degassed water is fed to a gasifier 103 to hold the total gas concn. near or lower than the saturation level of a cleaning soln. at a process temp., using flow rate controllers 104, 105 or one control mixing valve 106 or another blend measuring valve. The partial saturation level of the gas attained in the soln. is pref. approximately 60-98% of the perfect saturation at a given temp. and pressure. A nonreactive gas having a higher solubility in the soln. is used to obtain a high wafer cleaning effect.

公开(公告)号：JPH11265982A

公开(公告)日：1999-09-28

申请号：JP1275999

申请日：1999-01-21

Applicant: IBM ,  TOSHIBA CORP ,  SIEMENS AG

Inventor： ILG MATTHIAS ,  KLEINHENZ RICHARD L ,  NADAHARA SOUICHI ,  NUNEZ RONALD W ,  PENNER KLAUS ,  ROITHNER KLAUS ,  SRINIVASAN RADHIKA ,  SUGIMOTO SHIGEKI

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enable capacitors and the like to be arranged on a chip in closer disposition to each other, by a method wherein a trench is provided to a semiconductor substrate by anisotropic etching penetrating through other layers laminated between a photoresist layer and the semiconductor substrate. SOLUTION: A substrate 1 with a patterned photoresist layer is anisotropically etched, and a part of layers under the exposed photoresist pattern is selectively removed including a part of the semiconductor substrate 1 to form a required trench. After etching is finished, a residual BSG layer 40 is removed. The BSG layer 40 can be highly selectively removed to the substrate 1 and dielectric layers 10 and 20. Usually, the surface of the dielectric layer is left nearly flat through a BGS removal process. The substrate 1 with a trench is subjected to various well-known manufacturing techniques, whereby component elements on the basis of a trench or other devices which form a required integrated circuit can be manufactured.