公开(公告)号：WO02058117A3

公开(公告)日：2003-08-28

申请号：PCT/EP0201049

申请日：2002-01-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP ,  IBM FRANCE

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E III ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mu ) with a bottom etch stop layer (104), a composite bottom plate (110) having an aluminium layer below a TiN layer, an oxide capacitor dielectric (120), and a top plate (130) of TiN. The process involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Abstract translation: 在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以内）的区域，底部蚀刻停止层（104），在TiN层下方具有铝层的复合底板（110）， 氧化物电容器电介质（120）和TiN的顶板（130）。 该方法包括蚀刻顶板以留下电容器区域，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质 并完成氮化物盖层的穿透。

公开(公告)号：AT355614T

公开(公告)日：2006-03-15

申请号：AT02718080

申请日：2002-01-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E III ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：DE60218442D1

公开(公告)日：2007-04-12

申请号：DE60218442

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：DE60218442T2

公开(公告)日：2007-11-15

申请号：DE60218442

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.