2.
    发明专利
    未知

    公开(公告)号:DE10356956A1

    公开(公告)日:2004-07-22

    申请号:DE10356956

    申请日:2003-12-05

    Abstract: A test operation of a memory array permits changing the test vector during the test by controlling the contents of a test vector through at least two external terminals not used during the test to change from a first to a second test vector, both of said first and second test vectors being stored in a controllable register connected to the external terminals.

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