公开(公告)号：JP2001013670A

公开(公告)日：2001-01-19

申请号：JP2000160870

申请日：2000-05-30

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： SHAHIDO BUTTO ,  KAMIZU FARAHAPUURU ,  HAFFNER HENNING ,  MARK A RABIN ,  LAAS W LIEBMANN ,  DONALD J SAMUELS

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for enhancing the efficiency of the proximity correction of a pattern forming process in terms of given chip layout design, and constitution therefor. SOLUTION: This method includes a step G01 for describing the pattern forming process in accordance with at least one layout parameter, a step G03 for making the distribution of at least one parameter discrete, a step G05 for providing an error correction table linking the correction of layout with at least one parameter and a step G06 for correcting the layout by applying correction in the table to the layout at least once.

公开(公告)号：JP2005020008A

公开(公告)日：2005-01-20

申请号：JP2004187337

申请日：2004-06-25

Applicant: Infineon Technol North America Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  インフィニオン テクノロジーズ ノース アメリカ コーポレイション Infineon Technologies North America Corp.

Inventor： SHAHIDO BUTTO ,  ELLIS WAYNE F ,  GABRIC JOHN A

IPC: H01L29/423 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49

CPC classification number: H01L21/823437 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method which designs and manufactures a gate structure corrected by gate length proximity effect. SOLUTION: The device comprises a semiconductor substrate which has the array of gate conductors each of which has a length and a width, and comprises dummy gate conductors and functional gate conductors which extend in transverse direction. Further, in the substrate, the gate conductors extend in mostly parallel with each other in a widthwise direction, and they are periodically spaced apart a fixed distance in almost perpendicular direction to the widthwise direction. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过栅极长度邻近效应校正的栅极结构的设计和制造方法。 解决方案：该器件包括具有栅极导体阵列的半导体衬底，每个栅极导体具有长度和宽度，并且包括在横向方向上延伸的虚拟栅极导体和功能栅极导体。 此外，在基板中，栅极导体在宽度方向上大致平行地延伸，并且在与宽度方向大致垂直的方向上周期性地间隔开固定距离。 版权所有（C）2005，JPO＆NCIPI