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公开(公告)号：CA2132764A1
公开(公告)日：1996-03-24
申请号：CA2132764
申请日：1994-09-23
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J
IPC: G06F9/45
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公开(公告)号：CA2453777A1
公开(公告)日：2005-06-19
申请号：CA2453777
申请日：2003-12-19
Applicant: IBM CANADA
Inventor： TAL ARIE , BLAINEY ROBERT J
Abstract: There is disclosed a method and system for determining the bounds of generat ed software loops, where the relationships between split points and loop bounds are not known, or only partly known, at compile time. A "sub-range tree" is built with a root node representing the original software loop. Each sub-node represents a sub-range of the original software loop split by one or more split points. Each edge between nodes of the sub-range tree is marked with either a "then" (T) or "else" (E) marker, according to a predetermined scheme. Once the sub- range tree is built, a "path-from-root" is analyzed for each leaf node of the sub-range tree, and "dead" inductive control flow branches are identified and folded. The growth of software loop code based on the sub-range tree may be restricted by a predetermined code growth limit.
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公开(公告)号：CA2453685A1
公开(公告)日：2005-06-17
申请号：CA2453685
申请日：2003-12-17
Applicant: IBM CANADA
Inventor： VEZOLLE PASCAL , WHITE STEVEN W , ARCHAMBAULT ROCH G , O'CONNELL FRANCIS P , GAO YAOQING , MCCALPIN JOHN D , BLAINEY ROBERT J
Abstract: A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions formin g a loop including: determining static and dynamic characteristics for the instructions; selecti ng a modification factor for the instructions based on a number of separate equivalent sections formi ng a cache in a processor which is processing the instructions; and modifying the instructio ns to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.
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公开(公告)号：CA2166369C
公开(公告)日：2004-10-19
申请号：CA2166369
申请日：1995-12-29
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J
IPC: G06F9/45
Abstract: A system and method for determining alias information at the inter-compilation unit level of a compilation process includes the steps of determining anti-alias sets from the alias information provided by the first stage of th e compilation process, calculating pessimistic inter-compilation unit alias sets and refining these sets, after transitive closure as appropriate, with the anti-alias sets.
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公开(公告)号：CA2435148A1
公开(公告)日：2005-01-15
申请号：CA2435148
申请日：2003-07-15
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J , SILVERA RAUL E
Abstract: A system and method for lock caching for compound atomic operations (i.e. a read or write operation to more than one 4-byte word) on shared memory is provided. In a computer system including a memory shared among a plurality of processing entities, for example, multiple threads, a method of performing compound atomic operations comprises providing a pool of lacks for synchronizing access to the memory; assigning the locks among the plurality of entities to minimize lock contention; and performing the compound atomic operations using the assigned locks. Each lock may be assign ed in accordance with an address of the shared memory from the processing entity's compound atomic operations. Assigning locks may be performed in a manner to minimize concurrent atomic updates to the same or overlapping portions of th e shared memory. For example, the addresses of the memory from the compound atomic operations may be aliased in accordance with a known upper bound on the amou nt of the shared memory that may be affected by any atomic operation.
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Patent Agency Ranking
公开(公告)号：CA2419340A1
公开(公告)日：2004-08-20
申请号：CA2419340
申请日：2003-02-20
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J , ZHANG GUANSONG
IPC: G06F9/46 , G06F13/42 , G06F15/16 , G06F15/177
Abstract: The present invention provides an approach for barrier synchronization. The barrier has a first array of elements with each element of the first array having an associated process, and a second array of elements with each element of the second array having an associated process. Prior to use, the values or states of the elements in each array may be initialized. As each process finishes its phase and arrives at the barrier, it may update the val ue or state of its associated element in the first array. Each process may then proceed to spin at its associated element in the second array, waiting for that element to switch. When the values or states of the elements of the first array reach a predetermined value or state, an instruction is sent to all of the elements in the second array to switch their values or states, allowing all processes to leave.
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公开(公告)号：CA2132764C
公开(公告)日：1998-12-08
申请号：CA2132764
申请日：1994-09-23
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J
IPC: G06F9/45
Abstract: A novel method and system for optimizing the instructions produced by acompiler comprises examining pairs of load and pairs of store instructions to determine whether a pair of load or a pair of store instructions may be replaced with a single load or store instruction which utilizes the resources of the target data processing system more efficiently. The method and system are transparent to the user who may write the program source code in the conventional manner.
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公开(公告)号：CA2363182C
公开(公告)日：2006-06-06
申请号：CA2363182
申请日：2001-11-19
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J , HALL BRIAN C , WHITE STEVEN W
Abstract: A method, a computer or computer program product for automatically restructuring a program having arrays in inner loops to reduce an average penalty incurred for burst y cache miss patterns by spreading out the cache misses. The method may be used separately or in conjunction with methods for reducing the number of cache misses. The method determines a padding required for each array according to a proportion of the cache line size, to offset the starting points of the arrays relative to the start of a cache line memory access address for each array. Preferably, the starting points of the arrays that induce bursty cache misses are padded so that they are uniformly spaced from one another.
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公开(公告)号：CA2392122A1
公开(公告)日：2003-12-28
申请号：CA2392122
申请日：2002-06-28
Applicant: IBM CANADA
Inventor： TAL ARIE , BLAINEY ROBERT J
Abstract: The present invention is directed to a transformation technique for nested loops. A virtual iteration space may be determined based on an unroll factor (UF). The virtua l iteration space, which includes the actual iteration space, is formed such that, the virtual iteration space may be evenly divided by a selected UF. Once the virtual iteration space has been calculat ed or determined, the virtual iteration space is "cut" into regular portions by one or more unroll factors. Portions of the actual iteration space which do not fill the cut portions of the virtual iteration space or which fall outside these cuts which have been evenly divided by the unroll factor form a residue which is calculated. The portions of the actual iteration space which remain are also evenly divided by the unroll factor(s). An outer loop for this remaining portion of the actual iteration space is then unrolled. This unrolled portion forms a perfect nested loop. Accordingly, th e operations for the unrolled remaining portion of the actual iteration space when combined with the operations for the residue of the actual iteration space which was not evenly divided by the unroll factor is, in appropriate situations, semantically equivalent to the original nested loops . Aspects of the invention are applicable to rectangular andtriangular loop nests, and combinations thereof. Moreover, the invention is applicable to loops having n-dimensions.
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公开(公告)号：CA2363182A1
公开(公告)日：2003-05-19
申请号：CA2363182
申请日：2001-11-19
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J , HALL BRIAN C , WHITE STEVEN W
Abstract: A method, a computer or computer program product for automatically restructuring a program having arrays in inner loops to reduce an average penalty incurred for burst y cache miss patterns by spreading out the cache misses. The method may be used separately or in conjunction with methods for reducing the number of cache misses. The method determines a padding required for each array according to a proportion of the cache line size, to offset the starting points of the arrays relative to the start of a cache line memory access address for each array. Preferably, the starting points of the arrays that induce bursty cache misses are padded so that they are uniformly spaced from one another.
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