公开(公告)号：DE2340814A1

公开(公告)日：1975-03-06

申请号：DE2340814

申请日：1973-08-11

Applicant: IBM DEUTSCHLAND

Inventor： BAITINGER UTZ G DIPL ING DR ,  HAUG WERNER DIPL ING ,  ILLI MANFRED DIPL ING DR

IPC: G11C5/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/415 ,  G11C11/417 ,  G11C11/418 ,  H03M7/00 ,  G11C8/00

Abstract: For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders.

公开(公告)号：DE2340770A1

公开(公告)日：1975-02-27

申请号：DE2340770

申请日：1973-08-11

Applicant: IBM DEUTSCHLAND

Inventor： BAITINGER UTZ G DIPL ING DR ,  ILLI MANFRED DIPL ING DR ,  CLEMEN RAINER DIPL-ING ,  GANSSLESER KURT DIPL-ING ,  HAUG WERNER DIPL-ING ,  OLDERDISSEN ULRICH DIPL-ING

IPC: H03K5/02 ,  H03K19/017

Abstract: The junction point between the first two FETs is the circuit output; the first FET gate is connected to an input terminal, and the gate of the second is connected through a feed-back capacitor to the above junction point. The third FET is controlled by a control voltage derived from a pulse voltage applied to the input, and dynamically increased during the charge phase; the third FET gate is capacitively coupled to the input; or it is so connected to a voltage divider circuit, that a biasing voltage is applied to the coupling capacitor before the beginning of the feed-back capacitor charge.