公开(公告)号：DE2338388A1

公开(公告)日：1975-02-13

申请号：DE2338388

申请日：1973-07-28

Applicant: IBM DEUTSCHLAND

Inventor： G DIPL-PHYS DR FOLBERTH OTTO ,  G DIPL-ING DR BAITINGER UTZ ,  HAUG WERNER DIPL-ING ,  KROELL KARL-EUGEN DIPL-PHYS DR

IPC: H01L21/8234 ,  H01L21/331 ,  H01L27/06 ,  H01L27/088 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/78 ,  H01L29/76

公开(公告)号：DE2340770A1

公开(公告)日：1975-02-27

申请号：DE2340770

申请日：1973-08-11

Applicant: IBM DEUTSCHLAND

Inventor： BAITINGER UTZ G DIPL ING DR ,  ILLI MANFRED DIPL ING DR ,  CLEMEN RAINER DIPL-ING ,  GANSSLESER KURT DIPL-ING ,  HAUG WERNER DIPL-ING ,  OLDERDISSEN ULRICH DIPL-ING

IPC: H03K5/02 ,  H03K19/017

Abstract: The junction point between the first two FETs is the circuit output; the first FET gate is connected to an input terminal, and the gate of the second is connected through a feed-back capacitor to the above junction point. The third FET is controlled by a control voltage derived from a pulse voltage applied to the input, and dynamically increased during the charge phase; the third FET gate is capacitively coupled to the input; or it is so connected to a voltage divider circuit, that a biasing voltage is applied to the coupling capacitor before the beginning of the feed-back capacitor charge.

公开(公告)号：DE2309186A1

公开(公告)日：1974-09-05

申请号：DE2309186

申请日：1973-02-23

Applicant: IBM DEUTSCHLAND

Inventor： FEICHT ERWIN ,  HAUG WERNER DIPL-ING ,  REMSHARDT ROLF DIPL-ING DR ,  SCHETTLER HELMUT DIPL-ING

IPC: G11C11/41 ,  G11C11/414 ,  G11C11/419 ,  H03F3/45 ,  G11C7/00

Abstract: In a monolithic semiconductor storage the bit lines are selectively connected in pairs to the inputs of a read amplifier. In their separated state the potentials of the read lines (VB) and of the associated input lines of the read amplifier (VBS1, VBS2) show the same value and are derived from a common potential (VH). Potentials VB as well as VBS1 and VBS2 are derived via the same respective number of diode voltage drops from potential VH.

公开(公告)号：DE2131939A1

公开(公告)日：1972-12-28

申请号：DE2131939

申请日：1971-06-26

Applicant: IBM DEUTSCHLAND

Inventor： HAUG WERNER DIPL-ING ,  BAITINGER UTZ DIPL-ING DR

IPC: H03K5/02 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/096 ,  H03K19/08

Abstract: Disclosed is an inverter circuit consisting of a first field-effect transistor connected in series to a capacitive load and a second field-effect transistor connected in parallel to said load, whereby charging and discharging of the capacitive load are effected via the first and second field-effect transistor, respectively, and a defined potential is applied to the capacitive load via a third field-effect transistor when the first field-effect transistor is inhibited.