公开(公告)号：FR2328349A1

公开(公告)日：1977-05-13

申请号：FR7308009

申请日：1973-03-01

Applicant: IBM FRANCE

Inventor： LEBIZAY GERALD ,  COUDER ALAIN

IPC: G06F13/00 ,  H04Q11/04 ,  H04J3/08 ,  H04L5/14

Abstract: Two-way links communication capability between time-division multiplexed subsystems is provided via dual time division address and data busses correlated by a recirculating memory having sections respectively associated with the address busses. Addresses on the address busses are recognized by the individual subsystems and further decoded to gate data to and from the busses data according to time slots assigned to terminal devices in the subsystems. The dual bus arrangement provides a full-duplex link in the sense that there is simultaneous communication via the two data busses, one each way.

公开(公告)号：FR2296221A1

公开(公告)日：1976-07-23

申请号：FR7443561

申请日：1974-12-27

Applicant: IBM FRANCE

Inventor： BORIE JEAN-CLAUDE ,  COUDER ALAIN ,  DAUBY ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  LECHACZINSKY MICHEL

IPC: H04Q3/545 ,  G06F1/02 ,  G06F9/46 ,  G06F13/36 ,  G06F13/40 ,  G06F15/80 ,  G06F17/10 ,  H04Q11/04 ,  G06F7/00 ,  H04J6/00 ,  H04M7/00

Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.