公开(公告)号：DE3277054D1

公开(公告)日：1987-09-24

申请号：DE3277054

申请日：1982-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： BOISSEAU MARC ,  BORIE JEAN CLAUDE ,  CROISIER ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  ROSSI JEAN-PIERRE PHILIPPE

IPC: H04Q11/04 ,  H04Q11/06

公开(公告)号：FR2296221A1

公开(公告)日：1976-07-23

申请号：FR7443561

申请日：1974-12-27

Applicant: IBM FRANCE

Inventor： BORIE JEAN-CLAUDE ,  COUDER ALAIN ,  DAUBY ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  LECHACZINSKY MICHEL

IPC: H04Q3/545 ,  G06F1/02 ,  G06F9/46 ,  G06F13/36 ,  G06F13/40 ,  G06F15/80 ,  G06F17/10 ,  H04Q11/04 ,  G06F7/00 ,  H04J6/00 ,  H04M7/00

Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.

公开(公告)号：DE3275692D1

公开(公告)日：1987-04-16

申请号：DE3275692

申请日：1982-12-28

Applicant: IBM ,  IBM FRANCE

Inventor： AMBOISE MODESTE ,  DEMANGE MICHEL ,  LEBIZAY GERARD ,  MUNIER JEAN-MARIE ,  PEYRONNENC MICHEL HENRI PAUL

IPC: H04L5/22 ,  H04J3/06 ,  H04L12/42 ,  H04Q11/04 ,  H04L11/16 ,  H04L7/00

Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.